Datasheet

© 2009 Microchip Technology Inc. DS39761C-page 105
PIC18F2682/2685/4682/4685
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3 UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is inter-
rupted by a MCLR
Reset, or a WDT Time-out Reset
during normal operation, the user can check the
WRERR bit and rewrite the location(s) as needed.
6.5.4 PROTECTION AGAINST
SPURIOUS WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 24.0 “Special Features of the
CPU” for more detail.
6.6 Flash Program Operation During
Code Protection
See Section 24.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
PROGRAM_MEMORY
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
TBLPTRU
— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 51
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 51
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 51
TABLAT Program Memory Table Latch 51
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
EECON2 EEPROM Control Register 2 (not a physical register) 53
EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD 53
IPR2 OSCFIP
CMIP
(1)
— EEIP BCLIP HLVDIP TMR3IP ECCP1IP
(1)
53
PIR2 OSCFIF
CMIF
(1)
— EEIF BCLIF HLVDIF TMR3IF ECCP1IF
(1)
54
PIE2 OSCFIE
CMIE
(1)
— EEIE BCLIE HLVDIE TMR3IE ECCP1IE
(1)
54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices.