PIC18F2682/2685/4682/4685 Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D and nanoWatt Technology © 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F2682/2685/4682/4685 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D and nanoWatt Technology Power-Managed Modes: Peripheral Highlights: • • • • • • • • • • • • Run: CPU on, peripherals on Idle: CPU off, peripherals on Sleep: CPU off, peripherals off Idle mode currents down to 5.8 μA typical Sleep mode currents down to 0.1 μA typical Timer1 Oscillator: 1.1 μA, 32 kHz, 2V Watchdog Timer: 2.
PIC18F2682/2685/4682/4685 Pin Diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PIC18F2685 MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL PIC18F2682 28-Pin PDIP, SOIC RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/AN10 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA MCLR/VPP/RE3 RA0/AN0/CVREF RA1/AN1
PIC18F2682/2685/4682/4685 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2INRD2/PSP2/C2IN+ RD1/PSP1/C1INRD0/PSP0/C1IN+ RC3/SCK/SCL RC2/CCP1 RC1/T1OSI NC Pin Diagrams (Continued) 33 32 31 30 29 28 27 26 25 24 23 PIC18F4682 PIC18F4685 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS VDD RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT RE0/RD/AN5 RA5/AN4/SS/HLVDIN RA4/T0CKI RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2INRD2/PSP2/C2IN+ RD1/PSP1/C1INRD0/PSP0/C1IN+ RC3/SCK
PIC18F2682/2685/4682/4685 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Oscillator Configurations ............................................................................................................................................................ 25 3.0 Power-Managed Modes .............................................................
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PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 8 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • • • • PIC18F2682 PIC18F2685 PIC18F4682 PIC18F4685 This family of devices offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Enhanced Flash program memory.
PIC18F2682/2685/4682/4685 1.2 Other Special Features • Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-Programmability: These devices can write to their own program memory spaces under internal software control.
PIC18F2682/2685/4682/4685 TABLE 1-1: DEVICE FEATURES Features PIC18F2682 PIC18F2685 PIC18F4682 PIC18F4685 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz 80K 96K 80K 96K Program Memory (Instructions) 40960 49152 40960 49152 Data Memory (Bytes) 3328 3328 3328 3328 Data EEPROM Memory (Bytes) 1024 1024 1024 1024 19 19 20 20 Ports A, B, C, (E) Ports A, B, C, (E) 4 4 Program Memory (Bytes) Interrupt Sources I/O Ports Timers Ports A, B, C, D, E Ports A,
PIC18F2682/2685/4682/4685 FIGURE 1-1: PIC18F2682/2685 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> 31 Level Stack 4 BSR Address Latch STKPTR Program Memory (80/96 Kbytes) Data Latch 8 Instruction Bus <16> RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 Data Memory (3.
PIC18F2682/2685/4682/4685 FIGURE 1-2: PIC18F4682/4685 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Memory (3.
PIC18F2682/2685/4682/4685 TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RE3 MCLR Pin Number PDIP, SOIC I ST P I ST 9 I CLKI I RA7 OSC2/CLKO/RA6 OSC2 Buffer Type 1 VPP RE3 OSC1/CLKI/RA7 OSC1 Pin Type I/O Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input.
PIC18F2682/2685/4682/4685 TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP, SOIC Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREFRA2 AN2 VREF- 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI RA4 T0CKI 6 RA5/AN4/SS/HLVDIN RA5 AN4 SS HLVDIN 7 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I TTL Analog Analog Digital I/O.
PIC18F2682/2685/4682/4685 TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP, SOIC Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F2682/2685/4682/4685 TABLE 1-2: PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP, SOIC Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 11 RC1/T1OSI RC1 T1OSI 12 RC2/CCP1 RC2 CCP1 13 RC3/SCK/SCL RC3 SCK SCL 14 RC4/SDI/SDA RC4 SDI SDA 15 RC5/SDO RC5 SDO 16 RC6/TX/CK RC6 TX CK 17 RC7/RX/DT RC7 RX DT 18 I/O O I ST — ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.
PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RE3 MCLR Pin Number PDIP QFN 1 18 Pin Buffer TQFP Type Type 18 VPP RE3 OSC1/CLKI/RA7 OSC1 13 32 I ST P I ST 30 I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 14 33 Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input.
PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN RA0/AN0/CVREF RA0 AN0 CVREF 2 19 RA1/AN1 RA1 AN1 3 RA2/AN2/VREFRA2 AN2 VREF- 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI RA4 T0CKI 6 RA5/AN4/SS/HLVDIN RA5 AN4 SS HLVDIN 7 Pin Buffer TQFP Type Type Description PORTA is a bidirectional I/O port. 20 21 22 23 24 19 I/O I O TTL Analog Analog Digital I/O. Analog input 0. Analog comparator reference output.
PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN Pin Buffer TQFP Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 15 34 RC1/T1OSI RC1 T1OSI 16 RC2/CCP1 RC2 CCP1 17 RC3/SCK/SCL RC3 SCK 18 Pin Buffer TQFP Type Type Description PORTC is a bidirectional I/O port. 35 36 37 32 23 RC5/SDO RC5 SDO 24 RC6/TX/CK RC6 TX CK 25 RC7/RX/DT RC7 RX DT 26 42 43 44 1 ST — ST I/O I ST CMOS I/O I/O ST ST Digital I/O.
PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN Pin Buffer TQFP Type Type Description PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled.
PIC18F2682/2685/4682/4685 TABLE 1-3: PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN Pin Buffer TQFP Type Type Description PORTE is a bidirectional I/O port. RE0/RD/AN5 RE0 RD 8 25 25 AN5 RE1/WR/AN6/C1OUT RE1 WR 9 26 10 27 ST TTL I Analog I/O I ST TTL I O Analog TTL I/O I ST TTL I O Analog TTL Digital I/O. Read control for Parallel Slave Port (see also WR and CS pins). Analog input 5. 26 AN6 C1OUT RE2/CS/AN7/C2OUT RE2 CS I/O I Digital I/O.
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 24 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types PIC18F2682/2685/4682/4685 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. LP XT HS HSPLL Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL enabled 5. RC External Resistor/Capacitor with FOSC/4 output on RA6 6.
PIC18F2682/2685/4682/4685 TABLE 2-2: Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Typical Capacitor Values Tested: C1 C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 1 MHz 33 pF 33 pF 4 MHz 27 pF 27 pF 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized.
PIC18F2682/2685/4682/4685 2.4 RC Oscillator 2.5 For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The actual oscillator frequency is a function of several factors: • supply voltage • values of the external resistor (REXT) and capacitor (CEXT) • operating temperature Given the same device, operating voltage and temperature and component values, there will also be unit-to-unit frequency variations.
PIC18F2682/2685/4682/4685 2.6 Internal Oscillator Block The PIC18F2682/2685/4682/4685 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the device clock.
PIC18F2682/2685/4682/4685 REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0(1) R/W-0 INTSRC PLLEN (1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.
PIC18F2682/2685/4682/4685 2.7 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F2682/2685/ 4682/4685 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2682/2685/4682/4685 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available.
PIC18F2682/2685/4682/4685 2.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 2-2) controls several aspects of the device clock’s operation, both in full power operation and in power-managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source. The available clock sources are the primary clock (defined by the FOSC3:FOSC0 Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block.
PIC18F2682/2685/4682/4685 REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Inte
PIC18F2682/2685/4682/4685 2.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock.
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 34 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 3.0 POWER-MANAGED MODES 3.1.1 PIC18F2682/2685/4682/4685 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • Run modes • Idle modes • Sleep mode These categories define which portions of the device are clocked and sometimes, what speed.
PIC18F2682/2685/4682/4685 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • OSTS (OSCCON<3>) • IOFS (OSCCON<2>) • T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode.
PIC18F2682/2685/4682/4685 FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 T1OSI Q2 1 2 n-1 3 Q3 Q4 Q1 Q2 Q3 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 3-2: PC + 2 PC + 4 TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed PC PC + 2 PC + 4 OST
PIC18F2682/2685/4682/4685 If the IRCF bits were previously at a non-zero value or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set. primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-4). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch.
PIC18F2682/2685/4682/4685 3.3 Sleep Mode 3.4 The power-managed Sleep mode in the PIC18F2682/ 2685/4682/4685 devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch.
PIC18F2682/2685/4682/4685 3.4.1 PRI_IDLE MODE 3.4.2 This mode is unique among the three low-power Idle modes in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction.
PIC18F2682/2685/4682/4685 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP.
PIC18F2682/2685/4682/4685 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all.
PIC18F2682/2685/4682/4685 4.0 RESET The PIC18F2682/2685/4682/4685 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset during execution Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers.
PIC18F2682/2685/4682/4685 REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN:
PIC18F2682/2685/4682/4685 4.2 Master Clear Reset (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F2682/2685/4682/4685 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input.
PIC18F2682/2685/4682/4685 4.4 Brown-out Reset (BOR) PIC18F2682/2685/4682/4685 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits.
PIC18F2682/2685/4682/4685 4.5 Device Reset Timers 4.5.3 PIC18F2682/2685/4682/4685 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.
PIC18F2682/2685/4682/4685 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 4-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39761C-page 48 © 200
PIC18F2682/2685/4682/4685 FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD) FIGURE 4-7: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the Power-up Timer. © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 4.6 Reset State of Registers PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 4-3. These bits are used in software to determine the nature of the Reset. Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred.
PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TOSU 2682 2685 4682 4685 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2682 2685 4682 4685 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 2682 2685 4682 4685 ---0 00
PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt BSR 2682 2685 4682 4685 ---- 0000 ---- 0000 ---- uuuu INDF2 2682 2685 4682 4685 N/A N/A N/A Register POSTINC2 2682 2685 4682 4685 N/A N/A N/A POSTDEC2 2682 2685 4682 4685 N/A N/A N/A PREINC2 2682 2685 4682 4685 N/A N/A N/A PLUSW2 2682 2685 4682 4685
PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets ADCON2 2682 2685 4682 4685 0-00 0000 0-00 0000 CCPR1H 2682 2685 4682 4685 xxxx xxxx uuuu uuuu Register Wake-up via WDT or Interrupt u-uu uuuu uuuu uuuu CCPR1L 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 2682 2685 4682 4685 --00 0000 --00 0000 --uu uuuu ECCPR1H 2682 2685 46
PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register PIR2 PIE2 IPR1 PIR1 PIE1 Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt 2682 2685 4682 4685 00-0 0000 00-0 0000 uu-u uuuu(1) 2682 2685 4682 4685 0--0 000- 0--0 000- u--u uuu-(1) 2682 2685 4682 4685 00-0 0000 00-0 0000 uu-u uuuu 2682 2685 4682 4685 0--0 000- 0--0 000- u--u uuu- 2682 2685 4682 4685
PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt BRGCON3 2682 2685 4682 4685 00-- -000 00-- -000 uu-- -uuu BRGCON2 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu BRGCON1 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu CANCON 2682 2685 4682 4685 1000 000- 1000 000- uuuu uuu- CANSTAT 2682 2685 4682 468
PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt RXB1SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1CON 2682 2685 4682 4685 000- 0000 000- 0000 uuu- uuuu TXB0D7 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D6 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D5 2682 2685 4682 4685
PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TXB2D6 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D5 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D4 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D3 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D2 2682 2685 4682 4685 x
PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt RXF3SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF3SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF2SIDL 2682 2685 46
PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt B4D4(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4D3(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B4D1(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) Register B4D2 B4D0 2682
PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt B2D1(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B2D0(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu B2EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) B2EIDH 2682 2685 4682
PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt B0EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu B0EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu B0SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu (6) B0CON 2682 2685 46
PIC18F2682/2685/4682/4685 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt RXF13EIDL(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF13EIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu Register Applicable Devices (6) RXF13SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF13SIDH(6) 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uu
PIC18F2682/2685/4682/4685 5.0 MEMORY ORGANIZATION 5.1 There are three types of memory in PIC18 Enhanced microcontroller devices: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers.
PIC18F2682/2685/4682/4685 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18F2682/2685/4682/4685 5.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop returns a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bit.
PIC18F2682/2685/4682/4685 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset.
PIC18F2682/2685/4682/4685 5.2 PIC18 Instruction Cycle 5.2.1 5.2.2 An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18F2682/2685/4682/4685 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’ (see Section 5.1.1 “Program Counter”).
PIC18F2682/2685/4682/4685 5.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory.
PIC18F2682/2685/4682/4685 FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2682/2685/4682/4685 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 DS39761C-page 70 When a = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 GPR Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 1FFh 200h FFh 00h GPR FFh 00h 2FFh 300h GPR The BSR is ignored and the Access Bank is used.
PIC18F2682/2685/4682/4685 FIGURE 5-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 1 000h Data Memory 00h Bank 0 100h Bank 1 200h Bank 2 300h FFh 00h From Opcode(2) 7 1 1 1 1 1 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: 5.3.
PIC18F2682/2685/4682/4685 5.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these registers is given in Table 5-1 and Table 5-2.
PIC18F2682/2685/4682/4685 TABLE 5-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Name F7Fh — Address F5Fh Name CANCON_RO0 Address Name F3Fh CANCON_RO2 Address Name F1Fh RXM1EIDL RXM1EIDH F7Eh — F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh F7Dh — F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch — F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh — F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah — F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F79
PIC18F2682/2685/4682/4685 TABLE 5-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Name EFFh — Address Name EDFh — Address Name EBFh — Address Name E9Fh — EFEh — EDEh — EBEh — E9Eh — EFDh — EDDh — EBDh — E9Dh — EFCh — EDCh — EBCh — E9Ch — EFBh — EDBh — EBBh — E9Bh — EFAh — EDAh — EBAh — E9Ah — EF9h — ED9h — EB9h — E99h — EF8h — ED8h — EB8h — E98h — EF7h — ED7h — EB7h — E97h — EF6h — ED
PIC18F2682/2685/4682/4685 TABLE 5-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Name Address E7Fh CANCON_RO4 E7Eh CANSTAT_RO4 E7Dh B5D7(2) E6Fh Name CANCON_RO5 E6Eh CANSTAT_RO5 CANCON_RO6 Address Name E4Fh CANCON_RO7 E5Eh CANSTAT_RO6 B3D7(2) E4Dh B2D7(2) E6Ch B4D6 (2) E5Ch B3D6 (2) E4Ch B2D6(2) E6Bh B4D5(2) E5Bh B3D5(2) E4Bh B2D5(2) E6Ah B4D4(2) E5Ah B3D4(2) E4Ah B2D4(2) E69h B4D3 (2) E59h B3D3 (2) E49h B2D3(2) E68
PIC18F2682/2685/4682/4685 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Address Name DFFh — Address Name DDFh — Address Name DBFh — Address Name D9Fh — DFEh — DDEh — DBEh — D9Eh — DFDh — DDDh — DBDh — D9Dh — DFCh TXBIE DDCh — DBCh — D9Ch — DFBh — DDBh — DBBh — D9Bh — DFAh BIE0 DDAh — DBAh — D9Ah — DF9h — DD9h — DB9h — D99h — DF8h BSEL0 DD8h SDFLC DB8h — D98h — DF7h — DD7h — DB7h — D97
PIC18F2682/2685/4682/4685 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2682/2685/4682/4685 DEVICES (CONTINUED) Address Name D7Fh — D7Eh — D7Dh — D7Ch — D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH D71h RXF9SIDL D70h RXF9SIDH D6Fh — D6Eh — D6Dh — D6Ch — D6Bh RXF8EIDL D6Ah RXF8EIDH D69h RXF8SIDL D68h RXF8SIDH D67h RXF7EIDL D66h RXF7EIDH D65h RXF7
PIC18F2682/2685/4682/4685 TABLE 5-2: File Name TOSU REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) Bit 7 Bit 6 Bit 5 — — — Bit 4 Top-of-Stack Register High Byte (TOS<15:8>) TOSL Top-of-Stack Register Low Byte (TOS<7:0>) STKFUL STKUNF — PCLATU — — bit 21(1) Bit 2 Bit 1 Bit 0 Top-of-Stack Register Upper Byte (TOS<20:16>) TOSH STKPTR Bit 3 SP4 SP3 SP2 SP1 SP0 Holding Register for PC<20:16> Value on Details POR, BOR on page: ---0 0000 51, 64 0000 0000 51, 64 0000 0000 51, 64
PIC18F2682/2685/4682/4685 TABLE 5-2: File Name STATUS REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — — N OV Z DC C TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON Value on Details POR, BOR on page: ---x xxxx 52, 89 0000 0000 52, 151 xxxx xxxx 52, 151 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 52, 151 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 HLVD
PIC18F2682/2685/4682/4685 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 53, 233 SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 53, 233 RCREG EUSART Receive Register 0000 0000 53, 240 TXREG EUSART Transmit Register 0000 0000 53, 238 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0
PIC18F2682/2685/4682/4685 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 54, 134 PORTA RA7(6) RA6(6) RA5 RA4 RA3 RA2 RA1 RA0 xx00 0000 54, 131 ECANCON MDSEL1 MDSEL0 FIFOWM EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 TXERRCNT TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 RXERRCNT COMSTAT Mode 0 COMSTAT Mo
PIC18F2682/2685/4682/4685 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: RXB1D5 RXB1D57 RXB1D56 RXB1D55 RXB1D54 RXB1D53 RXB1D52 RXB1D51 RXB1D50 xxxx xxxx 55, 295 RXB1D4 RXB1D47 RXB1D46 RXB1D45 RXB1D44 RXB1D43 RXB1D42 RXB1D41 RXB1D40 xxxx xxxx 55, 295 RXB1D3 RXB1D37 RXB1D36 RXB1D35 RXB1D34 RXB1D33 RXB1D32 RXB1D31 RXB1D30 xxxx xxxx 55, 295 RXB1D2 RXB1D
PIC18F2682/2685/4682/4685 TABLE 5-2: File Name TXB1CON TXB2D7 REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0-00 56, 284 TXB2D77 TXB2D76 TXB2D75 TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 xxxx xxxx 56, 286 xxxx xxxx 57, 286 TXB2D6 TXB2D67 TXB2D66 TXB2D65 TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 TXB2D5 TXB2D57 TXB2D56 TXB2D5
PIC18F2682/2685/4682/4685 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RXF1SIDL SID2 SID1 RXF1SIDH SID10 SID9 SID0 — SID8 SID7 Value on Details POR, BOR on page: Bit 2 Bit 1 Bit 0 EXIDEN — EID17 EID16 xxx- x-xx 58, 305 SID6 SID5 SID4 SID3 xxxx xxxx 58, 306 RXF0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 58, 306 RXF0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 58, 30
PIC18F2682/2685/4682/4685 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: B4SIDL(8) Receive mode SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 58, 300 B4SIDL(8) Transmit mode SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 58, 300 B4SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 59, 299 B4CON(8) Receive mode RXFUL RXM1 RXRTRRO FILHIT
PIC18F2682/2685/4682/4685 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: xxxx xxxx 60, 301 B2EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 B2EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 60, 301 B2SIDL(8) Receive mode SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 58, 300 B2SIDL(8) Transmit mode SID2 SID1 SID0 — EXIDE — EID1
PIC18F2682/2685/4682/4685 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: B0DLC(8) Transmit mode — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 58, 304 xxxx xxxx 61, 301 B0EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 B0EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 61, 301 B0SIDL(8) Receive mode SID2 SID1 SID0 SRR EXID — EID17 E
PIC18F2682/2685/4682/4685 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: RXF12EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 62, 306 RXF12EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 62, 306 RXF12SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 62, 305 RXF12SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 62
PIC18F2682/2685/4682/4685 5.3.5 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed.
PIC18F2682/2685/4682/4685 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18F2682/2685/4682/4685 5.4.3.1 FSR Registers and the INDF Operand mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target.
PIC18F2682/2685/4682/4685 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value.
PIC18F2682/2685/4682/4685 5.5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds eight additional two-word commands to the existing PIC18 instruction set: ADDFSR, ADDULNK, CALLW, MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These instructions are executed as described in Section 5.2.4 “Two-Word Instructions”. 5.
PIC18F2682/2685/4682/4685 FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as the SFRs, or locations F60h to 0FFh (Bank 15) of data memory.
PIC18F2682/2685/4682/4685 5.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower half of Access RAM (00h to 7Fh) is mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user defined “window” that can be located anywhere in the data memory space.
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 96 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time.
PIC18F2682/2685/4682/4685 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. 6.
PIC18F2682/2685/4682/4685 REGISTER 6-1: R/W-x EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x EEPGD CFGS U-0 — R/W-0 FREE R/W-x (1) WRERR R/W-0 R/S-0 R/S-0 WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash
PIC18F2682/2685/4682/4685 6.2.2 TABLAT – TABLE LATCH REGISTER 6.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT.
PIC18F2682/2685/4682/4685 6.3 Reading the Flash Program Memory The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time.
PIC18F2682/2685/4682/4685 6.4 Erasing Flash Program Memory 6.4.1 The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word Erase in the Flash array is not supported. The sequence of events for erasing a block of internal program memory location is: 1. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased.
PIC18F2682/2685/4682/4685 6.5 Writing to Flash Program Memory The minimum programming block is 32 words or 64 bytes. Word or byte programming is not supported. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. Table writes are used internally to load the holding registers needed to program the Flash memory.
PIC18F2682/2685/4682/4685 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ;
PIC18F2682/2685/4682/4685 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF Required Sequence 6.5.2 EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EEPGD CFGS WREN GIE ; ; ; ; WR GIE WREN write 0AAh start program (CPU stall) re-enable interrupts disable write to memory 6.5.
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 106 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 7.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range.
PIC18F2682/2685/4682/4685 REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Fl
PIC18F2682/2685/4682/4685 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADRH:EEADR register pair, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).
PIC18F2682/2685/4682/4685 7.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal Data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 24.0 “Special Features of the CPU” for additional information. 7.
PIC18F2682/2685/4682/4685 TABLE 7-1: Name INTCON EEADRH REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 GIE/GIEH PEIE/GIEL — — Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF — — — — Bit 1 Bit 0 INT0IF RBIF Reset Values on page EEPROM Address Register High Byte 51 53 EEADR EEPROM Address Register Low Byte 53 EEDATA EEPROM Data Register 53 EECON2 EEPROM Control Register 2 (not a physical register) 53 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 53 IPR2 OSCF
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 112 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 8.0 8 x 8 HARDWARE MULTIPLIER 8.1 Introduction EXAMPLE 8-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register.
PIC18F2682/2685/4682/4685 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
PIC18F2682/2685/4682/4685 9.0 INTERRUPTS The PIC18F2682/2685/4682/4685 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress.
PIC18F2682/2685/4682/4685 FIGURE 9-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP Wake-up if in Sleep Mode INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Interrupt to CPU Vector to Location 0008h GIE/GIEH TMR1IF TMR1IE TMR1IP IPEN XXXXIF XXXXIE XXXXIP IPEN PEIE/GIEL IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral In
PIC18F2682/2685/4682/4685 9.1 INTCON Registers Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 9-1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F2682/2685/4682/4685 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0
PIC18F2682/2685/4682/4685 REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priorit
PIC18F2682/2685/4682/4685 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1, PIR2). REGISTER 9-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit, GIE (INTCON<7>).
PIC18F2682/2685/4682/4685 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CMIF(1) — EEIF BCLIF HLVDIF TMR3IF ECCP1IF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleare
PIC18F2682/2685/4682/4685 REGISTER 9-6: Mode 0 Mode 1,2 R/W-0 PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXB2IF TXB1IF(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXBnIF (1) TXB1IF R/W-0 TXB0IF (1) R/W-0 TXB0IF (1) R/W-0 R/W-0 RXB1IF RXB0IF R/W-0 R/W-0 RXBnIF FIFOWMIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear
PIC18F2682/2685/4682/4685 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F2682/2685/4682/4685 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE(1) — EEIE BCLIE HLVDIE TMR3IE ECCP1IE(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit(1) 1 = Enabled 0 = Disabled bit 5
PIC18F2682/2685/4682/4685 REGISTER 9-9: Mode 0 Mode 1 PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE TXB1IE(1) TXB0IE(1) RXB1IE RXB0IE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXBnIE TXB1IE(1) TXB0IE(1) RXBnIE FIFOWMIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit i
PIC18F2682/2685/4682/4685 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F2682/2685/4682/4685 REGISTER 9-11: R/W-1 IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 (1) OSCFIP CMIP U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit(1) 1 = High priori
PIC18F2682/2685/4682/4685 REGISTER 9-12: Mode 0 Mode 1,2 R/W-1 IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP R/W-1 (1) (1) TXB1IP TXB0IP R/W-1 R/W-1 (1) TXBnIP R/W-1 TXB1IP (1) TXB0IP R/W-1 R/W-1 RXB1IP RXB0IP R/W-1 R/W-1 RXBnIP FIFOWMIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
PIC18F2682/2685/4682/4685 9.5 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities.
PIC18F2682/2685/4682/4685 9.6 INTx Pin Interrupts 9.7 External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit INTxIE.
PIC18F2682/2685/4682/4685 10.0 I/O PORTS 10.1 Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC18F2682/2685/4682/4685 TABLE 10-1: PORTA I/O SUMMARY Pin Name RA0/AN0/CVREF Function I/O TRIS Buffer OUT 0 DIG LATA<0> data output. IN 1 TTL PORTA<0> data input. IN 1 ANA A/D input channel 0. Enabled on POR, this analog input overrides the digital input (read as clear – low level). CVREF(1) OUT x ANA Comparator voltage reference analog output. Enabling this analog output overrides the digital I/O (read as clear – low level). RA1 OUT 0 DIG LATA<1> data output.
PIC18F2682/2685/4682/4685 TABLE 10-2: Name PORTA SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 54 (1) LATA LATA7 TRISA TRISA7(1) LATA6(1) LATA Data Output Register (1) TRISA6 54 PORTA Data Direction Register 54 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52 CMCON(2) C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53 CVRCON(2) CVREN CVROE CVRR CVRSS CVR3 CV
PIC18F2682/2685/4682/4685 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped.
PIC18F2682/2685/4682/4685 TABLE 10-3: Pin Name PORTB I/O SUMMARY Function RB0/INT0/FLT0/AN10 RB0 RB1/INT1/AN8 RB2/INT2/CANTX RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD Legend: Note 1: Buffer Description OUT 0 DIG LATB<0> data output. IN 1 TTL PORTB<0> data input. Weak pull-up available only in this mode. External interrupt 0 input. INT0 IN 1 ST IN 1 ST AN10 IN 1 ANA A/D input channel 10. Enabled on POR, this analog input overrides the digital input (read as clear – low level).
PIC18F2682/2685/4682/4685 TABLE 10-4: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 54 LATB LATB Data Output Register 54 TRISB PORTB Data Direction Register 54 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE INTEDG0 INTEDG1 INTEDG2 RBIE TMR0IF INT0IF RBIF 51 — TMR0IP — RBIP 51 INTCON2 RBPU INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 51 ADCON1 —
PIC18F2682/2685/4682/4685 10.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped.
PIC18F2682/2685/4682/4685 TABLE 10-5: Pin Name RC0/T1OSO/ T13CKI RC1/T1OSI PORTC I/O SUMMARY Function I/O TRIS Buffer OUT 0 DIG LATC<0> data output. IN 1 ST PORTC<0> data input. T1OSO OUT x ANA T13CKI IN 1 ST Timer1/Timer3 clock input. OUT 0 DIG LATC<1> data output. IN 1 ST PORTC<1> data input. RC0 RC1 T1OSI RC2/CCP1 Description Timer1 oscillator output – overrides the TRIS<0> control when enabled.
PIC18F2682/2685/4682/4685 TABLE 10-6: Name PORTC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 54 LATC LATC Data Output Register 54 TRISC PORTC Data Direction Register 54 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 10.4 Note: PORTD, TRISD and LATD Registers PORTD is only available on PIC18F4682/ 4685 devices. PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F2682/2685/4682/4685 TABLE 10-7: Pin Name RD0/PSP0/ C1IN+ PORTD I/O SUMMARY Function RD0 0 DIG LATD<0> data output. 1 ST PORTD<0> data input. OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<0> control when enabled). IN 1 ANA Comparator 1 positive input B. Default on POR. This analog input overrides the digital input (read as clear – low level).
PIC18F2682/2685/4682/4685 TABLE 10-8: Name PORTD(1) SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 54 LATD(1) LATD Data Output Register 54 TRISD(1) PORTD Data Direction Register 54 TRISE(1) IBF OBF ECCP1CON(1) EPWM1M1 EPWM1M0 Legend: Note 1: IBOV PSPMODE EDC1B1 EDC1B0 — TRISE2 TRISE1 TRISE0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 54 53 — = unimplemented, read as ‘0’.
PIC18F2682/2685/4682/4685 10.5 PORTE, TRISE and LATE Registers Depending on the particular PIC18F2682/2685/4682/ 4685 device selected, PORTE is implemented in two different ways. For PIC18F4682/4685 devices, PORTE is a 4-bit wide port. Three pins (RE0/RD/AN5, RE1/WR/AN6/C1OUT and RE2/CS/AN7/C2OUT) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘0’s.
PIC18F2682/2685/4682/4685 REGISTER 10-1: TRISE REGISTER (PIC18F4682/4685 DEVICES ONLY) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: O
PIC18F2682/2685/4682/4685 TABLE 10-9: PORTE I/O SUMMARY Pin Name Function RE0/RD/AN5 RE0 MCLR/VPP/RE3 Legend: TRIS Buffer OUT 0 DIG Description LATE<0> data output. IN 1 ST PORTE<0> data input. RD IN 1 TTL PSP read enable input. AN5 IN 1 ANA A/D input channel 5. Enabled on POR, this analog input overrides the digital input (read as clear – low level). OUT 0 DIG LATE<1> data output. RE1/WR/AN6/C1OUT RE1 RE2/CS/AN7/C2OUT I/O IN 1 ST PORTE<1> data input.
PIC18F2682/2685/4682/4685 10.6 Note: Parallel Slave Port The Parallel Slave Port is only available on PIC18F4682/4685 devices. In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 10-1).
PIC18F2682/2685/4682/4685 FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 10-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 54 LATD (1) TRISD(1) (1)
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 148 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 11.0 TIMER0 MODULE The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection. It is both readable and writable.
PIC18F2682/2685/4682/4685 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected by clearing the T0CS bit (T0CON<5>). In Timer mode, the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
PIC18F2682/2685/4682/4685 11.3 Prescaler 11.3.1 An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS2:T0PS0 bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable.
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 152 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 12.
PIC18F2682/2685/4682/4685 12.1 Timer1 Operation cycle (Fosc/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter When Timer1 is enabled, the RC1/T1OSI and RC0/ T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
PIC18F2682/2685/4682/4685 12.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register.
PIC18F2682/2685/4682/4685 12.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD.
PIC18F2682/2685/4682/4685 EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h TMR1H TMR1L b’00001111’ T1OSC secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 158 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 13.0 TIMER2 MODULE 13.1 Timer2 Operation • 8-bit timer and period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4 and 1:16) • Software programmable postscaler (1:1 through 1:16) • Interrupt on TMR2 to PR2 match • Optional use as the shift clock for the MSSP module In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4).
PIC18F2682/2685/4682/4685 13.2 Timer2 Interrupt 13.3 Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/ postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
PIC18F2682/2685/4682/4685 14.0 TIMER3 MODULE The Timer3 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt on overflow • Module Reset on CCP1 Special Event Trigger REGISTER 14-1: A simplified block diagram of the Timer3 module is shown in Figure 14-1.
PIC18F2682/2685/4682/4685 14.1 Timer3 Operation cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled. Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter As with Timer1, the RC1/T1OSI and RC0/T1OSO/ T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
PIC18F2682/2685/4682/4685 14.2 Timer3 16-Bit Read/Write Mode 14.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 14-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register.
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 164 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 15.0 CAPTURE/COMPARE/PWM (CCP1) MODULES PIC18F2682/2685 devices have one CCP1 module. PIC18F4682/4685 devices have two CCP1 (Capture/ Compare/PWM) modules. CCP1, discussed in this chapter, implements standard Capture, Compare and Pulse-Width Modulation (PWM) modes. ECCP1 implements an Enhanced PWM mode. The ECCP1 implementation is discussed in Section 16.0 “Enhanced Capture/Compare/PWM (ECCP1) Module”.
PIC18F2682/2685/4682/4685 15.1 CCP1 Module Configuration Each Capture/Compare/PWM module is associated with a control register (CCP1CON or ECCP1CON) and a data register (CCPR1 or ECCPR1). The data register, in turn, is comprised of two 8-bit registers: CCPR1L or ECCPR1L (low byte) and CCPR1H or ECCPR1H (high byte). All registers are both readable and writable. 15.1.1 CCP1 MODULES AND TIMER RESOURCES The CCP1 modules utilize Timers 1, 2 or 3, depending on the mode selected.
PIC18F2682/2685/4682/4685 15.2 Capture Mode In Capture mode, the CCPR1H:CCPR1L (or ECCPR1H:ECCPR1L) register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the CCP1/ECCP1 pin (RC2 for 28/40/44-pin devices and RD4 for 40/44-pin devices). An event is defined as one of the following: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge The event is selected by the mode select bits, CCP1M3:CCP1M0 (CCP1CON<3:0>).
PIC18F2682/2685/4682/4685 FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set CCP1IF T3ECCP1 CCP1 pin Prescaler ÷ 1, 4, 16 and Edge Detect Q1:Q4 ECCP1CON<3:0> 4 4 Set ECCP1IF TMR3L TMR3 Enable CCPR1H T3ECCP1 CCP1CON<3:0> TMR3H CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L 4 T3CCP1 T3ECCP1 TMR3 Enable ECCP1 pin Prescaler ÷ 1, 4, 16 and Edge Detect ECCPR1H ECCPR1L TMR1 Enable T3ECCP1 T3CCP1 DS39761C-page 168 TMR1H TMR1L © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 15.3 Compare Mode 15.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCP1 pin can be: Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP1 module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. • • • • 15.3.
PIC18F2682/2685/4682/4685 TABLE 15-3: Name REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Reset Values on page Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 IPEN SBOREN(2) — RI TO PD POR BOR 52 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR2
PIC18F2682/2685/4682/4685 15.4 PWM Mode FIGURE 15-4: In Pulse-Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the RC2 output latch to the default low level. This is not the PORTC I/O data latch. Figure 15-3 shows a simplified block diagram of the CCP1 module in PWM mode.
PIC18F2682/2685/4682/4685 The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. EQUATION 15-3: PWM Resolution (max) = When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Note: The maximum PWM resolution (bits) for a given PWM frequency is given by the equation.
PIC18F2682/2685/4682/4685 TABLE 15-5: Name REGISTERS ASSOCIATED WITH PWM AND TIMER2 Bit 7 INTCON RCON Reset Values on page Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 IPEN SBOREN(2) — RI TO PD POR BOR 52 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 TRISB PORTB D
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 174 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 16.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP1) MODULE Note: The ECCP1 module is implemented only in PIC18F4682/4685 (40/44-pin) devices. In PIC18F4682/4685 devices, ECCP1 is implemented as a standard CCP1 module with Enhanced PWM capabilities. These include the provision for 2 or 4 output channels, user-selectable polarity, dead-band control and automatic shutdown and restart. The REGISTER 16-1: enhanced features are discussed in detail in Section 16.4 “Enhanced PWM Mode”.
PIC18F2682/2685/4682/4685 In addition to the expanded range of modes available through the ECCP1CON register, the ECCP1 module has two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: • ECCP1DEL (Dead-Band Delay) • ECCP1AS (Auto-Shutdown Configuration) 16.1 ECCP1 Outputs and Configuration The Enhanced CCP1 module may have up to four PWM outputs, depending on the selected operating mode.
PIC18F2682/2685/4682/4685 16.4 Enhanced PWM Mode 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation. The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCP1 module and offers up to four outputs, designated P1A through P1D.
PIC18F2682/2685/4682/4685 16.4.2 PWM DUTY CYCLE EQUATION 16-3: The PWM duty cycle is specified by writing to the ECCPR1L register and to the ECCP1CON<5:4> bits. Up to 10-bit resolution is available. The ECCPR1L contains the eight MSbs and the ECCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by ECCPR1L:ECCP1CON<5:4>. The PWM duty cycle is calculated by the following equation. ( log FOSC FPWM PWM Resolution (max) = log(2) Note: EQUATION 16-2: 16.4.
PIC18F2682/2685/4682/4685 FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) ECCP1CON <7:6> 00 (Single Output) SIGNAL 0 PR2 + 1 Duty Cycle Period P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 ECCP1CON <7:6> 00 (Single Output) Period P1A
PIC18F2682/2685/4682/4685 16.4.4 HALF-BRIDGE MODE FIGURE 16-4: In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 16-4). This mode can be used for half-bridge applications, as shown in Figure 16-5, or for full-bridge applications where four power switches are being modulated with two PWM signals.
PIC18F2682/2685/4682/4685 16.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 16-6. FIGURE 16-6: P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4>, PORTD<5>, PORTD<6> and PORTD<7> data latches.
PIC18F2682/2685/4682/4685 FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F268X/468X FET Driver QA QC FET Driver P1A Load P1B FET Driver P1C FET Driver QB QD VP1D 16.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the EPWM1M1 bit in the ECCP1CON register allows the user to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle.
PIC18F2682/2685/4682/4685 FIGURE 16-8: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: 2: The direction bit in the ECCP1 Control register (ECCP1CON<7>) is written any time during the PWM cycle. When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value.
PIC18F2682/2685/4682/4685 16.4.6 Note: PROGRAMMABLE DEAD-BAND DELAY Programmable dead-band delay is not implemented in PIC18F2682/2685 devices with standard CCP1 modules. In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on.
PIC18F2682/2685/4682/4685 REGISTER 16-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONFIGURATION REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP1 Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP1
PIC18F2682/2685/4682/4685 16.4.7.1 Auto-Shutdown and Auto-Restart 16.4.8 The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 16-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCPASE bit is cleared.
PIC18F2682/2685/4682/4685 16.4.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. 2. 3. 4. 5. 6. 7. 8. 9. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. Set the PWM period by loading the PR2 register.
PIC18F2682/2685/4682/4685 TABLE 16-3: Name REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Bit 7 Reset Values on page Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 IPEN SBOREN(3) — RI TO PD POR BOR 52 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 INTCON R
PIC18F2682/2685/4682/4685 17.0 17.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC18F2682/2685/4682/4685 17.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. The MSSP module has four registers for SPI mode operation. These are: In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
PIC18F2682/2685/4682/4685 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 WCOL SSPOV(1) R/W-0 (2) SSPEN R/W-0 CKP R/W-0 SSPM3 (3) R/W-0 SSPM2 (3) R/W-0 SSPM1 (3) R/W-0 SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitt
PIC18F2682/2685/4682/4685 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
PIC18F2682/2685/4682/4685 17.3.3 ENABLING SPI I/O 17.3.4 To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
PIC18F2682/2685/4682/4685 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC18F2682/2685/4682/4685 17.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit (SSPCON1<4>).
PIC18F2682/2685/4682/4685 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 7 bit 6 bit
PIC18F2682/2685/4682/4685 17.3.8 OPERATION IN POWER-MANAGED MODES 17.3.9 In SPI Master mode, module clocks may be operating at a different speed than when in full power mode. In the case of Sleep mode, all clocks are halted. In most power-managed modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTOSC source. See Section 2.7 “Clock Sources and Oscillator Switching” for additional information.
PIC18F2682/2685/4682/4685 17.4 I2C Mode 17.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC18F2682/2685/4682/4685 REGISTER 17-3: R/W-0 SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 SMP CKE R-0 R-0 R-0 D/A (1) (1) P S R-0 R/W (2,3) R-0 R-0 UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enable
PIC18F2682/2685/4682/4685 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C
PIC18F2682/2685/4682/4685 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in
PIC18F2682/2685/4682/4685 17.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I 2C operation.
PIC18F2682/2685/4682/4685 17.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON1<6>) is set.
DS39761C-page 204 CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
© 2009 Microchip Technology Inc.
DS39761C-page 206 4 1 5 0 7 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) CKP 3 1 Cleared in software 2 1 SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 5 A4 A3 6 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A2 A1 Cleared in s
© 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 17.4.4 CLOCK STRETCHING Both 7 and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 17.4.4.
PIC18F2682/2685/4682/4685 17.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 17-12: already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
DS39761C-page 210 CKP SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs
© 2009 Microchip Technology Inc. 2 1 UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
PIC18F2682/2685/4682/4685 17.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18F2682/2685/4682/4685 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC18F2682/2685/4682/4685 17.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
PIC18F2682/2685/4682/4685 17.4.7 BAUD RATE 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC18F2682/2685/4682/4685 17.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 17-18). Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high).
PIC18F2682/2685/4682/4685 17.4.8 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
PIC18F2682/2685/4682/4685 17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting.
PIC18F2682/2685/4682/4685 17.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106).
DS39761C-page 220 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Transmitting
© 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 17.4.12 ACKNOWLEDGE SEQUENCE TIMING 17.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to 0.
PIC18F2682/2685/4682/4685 17.4.14 SLEEP OPERATION 17.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 17.4.15 Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master asserts a ‘0’.
PIC18F2682/2685/4682/4685 17.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 17-26). SCL is sampled low before SDA is asserted low (Figure 17-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 17-28).
PIC18F2682/2685/4682/4685 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC18F2682/2685/4682/4685 17.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 17-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC18F2682/2685/4682/4685 17.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 17-31).
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 228 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 18.0 ENHANCED UNIVERSAL SYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
PIC18F2682/2685/4682/4685 REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F2682/2685/4682/4685 REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset)
PIC18F2682/2685/4682/4685 REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG
PIC18F2682/2685/4682/4685 18.1 Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free-running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also control the baud rate. In Synchronous mode, BRGH is ignored.
PIC18F2682/2685/4682/4685 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error — — — — — 1.221 2.441 1.73 255 9.615 0.16 64 Actual Rate (K) % Error 0.3 1.2 — — 2.4 9.6 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error — 1.73 — 255 — 1.202 2.404 0.16 129 9.766 1.73 31 SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error — 0.16 — 129 — 1.
PIC18F2682/2685/4682/4685 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error FOSC = 10.000 MHz (decimal) Actual Rate (K) SPBRG value % Error FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error SPBRG value SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1.2 1.200 0.02 2082 1.
PIC18F2682/2685/4682/4685 18.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 18-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. While the ABD sequence takes place, the EUSART state machine is held in Idle.
PIC18F2682/2685/4682/4685 FIGURE 18-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh RX pin 0000h 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto-Cleared Set by User ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
PIC18F2682/2685/4682/4685 18.2 EUSART Asynchronous Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and the TXIF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF will be set regardless of the state of TXIE; it cannot be cleared in software.
PIC18F2682/2685/4682/4685 FIGURE 18-4: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 18-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 2 Word 1 BRG Output (Shift Clock) TX (pin) TXIF bit (Interrupt Reg. Flag) Start bit bit 1 1 TCY TRMT bit (Transmit Shift Reg.
PIC18F2682/2685/4682/4685 18.2.2 EUSART ASYNCHRONOUS RECEIVER 18.2.3 The receiver block diagram is shown in Figure 18-6. The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F2682/2685/4682/4685 FIGURE 18-7: ASYNCHRONOUS RECEPTION Start bit RX (pin) bit 0 bit 7/8 Stop bit bit 1 Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG bit 7/8 RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set.
PIC18F2682/2685/4682/4685 18.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>).
PIC18F2682/2685/4682/4685 18.2.5 BREAK CHARACTER SEQUENCE The Enhanced EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data.
PIC18F2682/2685/4682/4685 18.3 EUSART Synchronous Master Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF is set regardless of the state of enable bit TXIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG register.
PIC18F2682/2685/4682/4685 FIGURE 18-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 18-7: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) AD
PIC18F2682/2685/4682/4685 18.3.2 EUSART SYNCHRONOUS MASTER RECEPTION 3. 4. 5. 6. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8.
PIC18F2682/2685/4682/4685 18.4 EUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 18.4.1 EUSART SYNCHRONOUS SLAVE TRANSMIT 2. 3. 4. 5. 6.
PIC18F2682/2685/4682/4685 18.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep or any Idle mode, and bit SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
PIC18F2682/2685/4682/4685 19.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) converter module has 8 inputs for the PIC18F2682/2685 devices and 11 for the PIC18F4682/4685 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number.
PIC18F2682/2685/4682/4685 REGISTER 19-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W-q(1) R/W-q(1) R/W-q(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared PCFG3: PCFG0 AN4 AN3 AN2 AN1 AN0 PCFG3:PCFG0: A/D Port Configuration Control bits: AN5(2) bit 3-0 AN6(2) VCFG0: Voltage Reference Configuration bit (VREF+ source) 1
PIC18F2682/2685/4682/4685 REGISTER 19-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20
PIC18F2682/2685/4682/4685 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF-/CVREF pins. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input, or as a digital I/O.
PIC18F2682/2685/4682/4685 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine acquisition time, see Section 19.1 “A/D Acquisition Requirements”.
PIC18F2682/2685/4682/4685 19.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 19-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F2682/2685/4682/4685 19.2 Selecting and Configuring Automatic Acquisition Time 19.3 The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit.
PIC18F2682/2685/4682/4685 19.4 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part, by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started.
PIC18F2682/2685/4682/4685 19.6 A/D Conversions Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers).
PIC18F2682/2685/4682/4685 19.7 Use of the ECCP1 Trigger An A/D conversion can be started by the “Special Event Trigger” of the ECCP1 module. This requires that the ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero.
PIC18F2682/2685/4682/4685 20.0 COMPARATOR MODULE Note: Comparators are only available in 40/44-pin devices (PIC18F4682/4685). The CMCON register (Register 20-1) selects the comparator input and output configuration. Block diagrams of the various comparator configurations are shown in Figure 20-1. The analog comparator module contains two comparators that can be configured in a variety of ways.
PIC18F2682/2685/4682/4685 20.1 Comparator Configuration There are eight modes of operation for the comparators, shown in Figure 20-1. Bits CM2:CM0 of the CMCON register are used to select these modes. The TRISA register controls the data direction of the comparator pins for each mode.
PIC18F2682/2685/4682/4685 20.2 Comparator Operation 20.3.2 A single comparator is shown in Figure 20-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
PIC18F2682/2685/4682/4685 + To RE1 or RE2 pin - Port pins COMPARATOR OUTPUT BLOCK DIAGRAM MULTIPLEX FIGURE 20-3: D Q Bus Data CxINV Read CMCON EN D Q EN CL From other Comparator Reset 20.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
PIC18F2682/2685/4682/4685 20.9 Analog Input Connection Considerations range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. A simplified circuit for an analog input is shown in Figure 20-4.
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 264 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 21.0 COMPARATOR VOLTAGE REFERENCE MODULE Note: Comparators are only available in 40/44-pin devices (PIC18F4682/4685). The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram is of the module shown in Figure 21-1.
PIC18F2682/2685/4682/4685 FIGURE 21-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ VDD CVRSS = 1 8R CVRSS = 0 CVR3:CVR0 R CVREN R R 16-to-1 MUX R 16 Steps R CVREF R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 21.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 21-1) keep CVREF from approaching the reference source rails.
PIC18F2682/2685/4682/4685 FIGURE 21-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F4682/4685 CVREF Module R(1) Voltage Reference Output Impedance + – RA0 CVREF Output Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 268 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 22.0 HIGH/LOW-VOLTAGE DETECT (HLVD) PIC18F2682/2685/4682/4685 devices have a High/ Low-Voltage Detect module (HLVD). This is a programmable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set.
PIC18F2682/2685/4682/4685 The module is enabled by setting the HLVDEN bit. Each time that the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit and is used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. event, depending on the configuration of the module.
PIC18F2682/2685/4682/4685 22.2 HLVD Setup The following steps are needed to set up the HLVD module: 1. 2. 3. 4. 5. 6. Disable the module by clearing the HLVDEN bit (HLVDCON<4>). Write the value to the HLVDL3:HLVDL0 bits that select the desired HLVD trip point. Set the VDIRMAG bit to detect high voltage (VDIRMAG = 1) or low voltage (VDIRMAG = 0). Enable the HLVD module by setting the HLVDEN bit. Clear the HLVD interrupt flag (PIR2<2>), which may have been set from a previous interrupt.
PIC18F2682/2685/4682/4685 FIGURE 22-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VLVD VDD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VLVD VDD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists Applications In many applications, the ability to detect a drop below, or rise above a particular threshol
PIC18F2682/2685/4682/4685 22.6 Operation During Sleep 22.7 When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 22-1: Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off.
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 274 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 23.0 ECAN™ TECHNOLOGY PIC18F2682/2685/4682/4685 devices contain an Enhanced Controller Area Network (ECAN) module. The ECAN module is fully backward compatible with the CAN module available in PIC18CXX8 and PIC18FXX8 devices. The Controller Area Network (CAN) module is a serial interface which is useful for communicating with other peripherals or microcontroller devices. This interface, or protocol, was designed to allow communications within noisy environments.
PIC18F2682/2685/4682/4685 BUFFERS 16 – 4 to 1 MUXs MESSAGE MSGREQ ABTF MLOA TXERR MTXBUFF MSGREQ ABTF MLOA TXERR MTXBUFF TXB2 MESSAGE TXB1 MESSAGE MSGREQ ABTF MLOA TXERR MTXBUFF TXB0 A c c e p t Acceptance Filters (RXF0-RXF05) MODE 0 Acceptance Filters (RXF06-RXF15) MODE 1, 2 MODE 0 2 RX Buffers Message Queue Control Transmit Byte Sequencer VCC Acceptance Mask RXM0 CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask RXM1 FIGURE 23-1: RXF15 Identifier Data Field M A B Rcv Byte
PIC18F2682/2685/4682/4685 23.2 Note: CAN Module Registers Not all CAN registers are available in the Access Bank. There are many control and data registers associated with the CAN module. For convenience, their descriptions have been grouped into the following sections: • • • • • • • 23.2.1 CAN CONTROL AND STATUS REGISTERS The registers described in this section control the overall operation of the CAN module and show its operational status.
PIC18F2682/2685/4682/4685 REGISTER 23-1: Mode 0 Mode 1 Mode 2 CANCON: CAN CONTROL REGISTER R/W-1 R/W-0 R/W-0 R/S-0 R/W-0 R/W-0 R/W-0 U-0 REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 — R/W-1 R/W-0 R/W-0 R/S-0 U0 U-0 U-0 U-0 REQOP2 REQOP1 REQOP0 ABAT — — — — R/W-1 R/W-0 R/W-0 R/S-0 R-0 R-0 R-0 R-0 REQOP2 REQOP1 REQOP0 ABAT FP3 FP2 FP1 FP0 bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value a
PIC18F2682/2685/4682/4685 REGISTER 23-2: Mode 0 Mode 1,2 CANSTAT: CAN STATUS REGISTER R-1 R-0 R-0 (1) (1) OPMODE2 OPMODE1 OPMODE0(1) R-0 — R-0 ICODE3 R-1 R-0 R-0 R-0 R-0 OPMODE2(1) OPMODE1(1) OPMODE0(1) EICODE4 EICODE3 bit 7 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set R-0 ICODE2 R-0 ICODE1 R-0 EICODE2 R-0 EICODE1 U-0 — R-0 EICODE0 bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown OPMODE2:OPMODE0: Operation Mode Status bits(1) 111
PIC18F2682/2685/4682/4685 EXAMPLE 23-1: CHANGING TO CONFIGURATION MODE ; Request Configuration mode. MOVLW B’10000000’ ; Set to Configuration Mode. MOVWF CANCON ; A request to switch to Configuration mode may not be immediately honored. ; Module will wait for CAN bus to be idle before switching to Configuration Mode. ; Request for other modes such as Loopback, Disable etc. may be honored immediately. ; It is always good practice to wait and verify before continuing.
PIC18F2682/2685/4682/4685 EXAMPLE 23-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED) ErrorInterrupt BCF PIR3, ERRIF ; Clear the interrupt flag … ; Handle error.
PIC18F2682/2685/4682/4685 REGISTER 23-3: ECANCON: ENHANCED CAN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 MDSEL1(1) MDSEL0(1) FIFOWM(2) EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 MDSEL1:MDSEL0: Mode Select bits(1) 00 = Legacy mode (Mode 0, default) 01 = Enhanced Legacy mode (Mode 1) 10 = Enhanced FIFO
PIC18F2682/2685/4682/4685 REGISTER 23-4: Mode 0 Mode 1 Mode 2 COMSTAT: COMMUNICATION STATUS REGISTER R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 — RXBnOVFL TXB0 TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 TXBO TXBP RXBP TXWARN RXWARN EWARN FIFOEMPTY RXBnOVFL bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n =
PIC18F2682/2685/4682/4685 23.2.2 DEDICATED CAN TRANSMIT BUFFER REGISTERS This section describes the dedicated CAN Transmit Buffer registers and their associated control registers.
PIC18F2682/2685/4682/4685 REGISTER 23-6: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown SID10:SID3: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0) Extended Identifier bits EID28:EID2
PIC18F2682/2685/4682/4685 REGISTER 23-9: TXBnEIDL: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown EID7:EID0: Extended Identifier bits (not used when transmitting standard identifier message) REGISTER
PIC18F2682/2685/4682/4685 REGISTER 23-11: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS [0 ≤ n ≤ 2] U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmit Remote Frame Transmission Request bit 1 = Transmitted message will have TXRTR bit set 0 = Transmitted m
PIC18F2682/2685/4682/4685 EXAMPLE 23-3: TRANSMITTING A CAN MESSAGE USING BANKED METHOD ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. And since we want banked method, we need to make sure ; that correct bank is selected. BANKSEL TXB0CON ; One BANKSEL in beginning will make sure that we are ; in correct bank for rest of the buffer access.
PIC18F2682/2685/4682/4685 EXAMPLE 23-4: TRANSMITTING A CAN MESSAGE USING WIN BITS ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. Use WIN bits to map it to RXB0 area. MOVF CANCON, W ; WIN bits are in lower 4 bits only. Read CANCON ; register to preserve all other bits. If operation ; mode is already known, there is no need to preserve ; other bits.
PIC18F2682/2685/4682/4685 23.2.3 DEDICATED CAN RECEIVE BUFFER REGISTERS This section shows the dedicated CAN Receive Buffer registers with their associated control registers.
PIC18F2682/2685/4682/4685 REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED) bit 2 Mode 0: RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 Mode 1, 2: FILHIT2: Filter Hit bit 2 This bit combines with other bits to form filter acceptance bits <4:0>.
PIC18F2682/2685/4682/4685 REGISTER 23-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER Mode 0 Mode 1,2 R/C-0 RXFUL(1) R/W-0 RXM1 R/W-0 RXM0 U-0 — R-0 RXRTRRO R/W-0 FILHIT2 R-0 FILHIT1 R-0 FILHIT0 R/C-0 RXFUL(1) bit 7 R/W-0 RXM1 R-0 RTRRO R-0 FILHIT4 R-0 FILHIT3 R-0 FILHIT2 R-0 FILHIT1 R-0 FILHIT0 bit 0 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5 bit 4 bit 3 Note 1: C = Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is clea
PIC18F2682/2685/4682/4685 REGISTER 23-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER (CONTINUED) bit 2-0 Note 1: Mode 0: FILHIT2:FILHIT0: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1.
PIC18F2682/2685/4682/4685 REGISTER 23-16: RXBnSIDL: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 1] R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID2:SID0: Standard Identifier bits (if EXID = 0) Extended Identifier bits EID20:EID18 (if EXID = 1).
PIC18F2682/2685/4682/4685 REGISTER 23-19: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS [0 ≤ n ≤ 1] U-0 R-x R-x R-x R-x R-x R-x R-x — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = Remote transfer request 0 = No remote transfer request bit 5 RB1: Reserv
PIC18F2682/2685/4682/4685 REGISTER 23-21: RXERRCNT: RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown REC7:REC0: Receive Error Counter bits This register contains the receive error value as defined by the CAN specifications.
PIC18F2682/2685/4682/4685 23.2.3.1 Programmable TX/RX and Auto-RTR Buffers The ECAN module contains 6 message buffers that can be programmed as transmit or receive buffers. Any of these buffers can also be programmed to automatically handle RTR messages. Note: These registers are not used in Mode 0.
PIC18F2682/2685/4682/4685 REGISTER 23-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0) = 1](1) R/W-0 TXBIF R-0 (3) TXABT R-0 (3) TXLARB R-0 (3) R/W-0 (3) TXERR (2,4) TXREQ R/W-0 RTREN R/W-0 TXPRI1 (5) R/W-0 TXPRI0(5) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TXBIF: Transmit Buffer Interrupt Flag bit(3) 1 = A message
PIC18F2682/2685/4682/4685 REGISTER 23-24: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown SID10:SID3: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0) Extended
PIC18F2682/2685/4682/4685 REGISTER 23-26: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0) = 0](1) R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID2:SID0: Standard Identifier bits (if EXID = 0) Extended Identifier bits EID20:EID18
PIC18F2682/2685/4682/4685 REGISTER 23-28: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID15:EID8: Extended Identifier bits These registers are available in
PIC18F2682/2685/4682/4685 REGISTER 23-31: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID7:EID0: Extended Identifier bits These registers are avail
PIC18F2682/2685/4682/4685 REGISTER 23-34: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL) = 0](1) U-0 R-x R-x R-x R-x R-x R-x R-x — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = This is a remote transmission request
PIC18F2682/2685/4682/4685 REGISTER 23-35: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL) = 1](1) U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmitter Remote Transmission Request bit 1 = Transmitted message will hav
PIC18F2682/2685/4682/4685 23.2.3.2 Message Acceptance Filters and Masks This section describes the message acceptance filters and masks for the CAN receive buffers.
PIC18F2682/2685/4682/4685 REGISTER 23-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID15:EID8: Extended Identifier Filter bits Registers RXF6EIDH:RXF15EIDH ar
PIC18F2682/2685/4682/4685 REGISTER 23-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK REGISTERS, LOW BYTE [0 ≤ n ≤ 1] R/W-x R/W-x SID2 SID1 R/W-x SID0 U-0 R/W-0 (1) — EXIDEN U-0 R/W-x R/W-x — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID2:SID0: Standard Identifier Mask bits or Extended Identifier Mask bits EID20:EID18 bit 4
PIC18F2682/2685/4682/4685 REGISTER 23-45: RXFCONn: RECEIVE FILTER CONTROL REGISTER n [0 ≤ n ≤ 1](1) RXFCON0 RXFCON1 R/W-0 RXF7EN R/W-0 RXF6EN R/W-1 RXF5EN R/W-1 RXF4EN R/W-1 RXF3EN R/W-1 RXF2EN R/W-1 RXF1EN R/W-1 RXF0EN R/W-0 RXF15EN bit 7 R/W-0 RXF14EN R/W-0 RXF13EN R/W-1 R/W-0 RXF12EN RXF11EN R/W-0 RXF10EN R/W-0 RXF9EN R/W-0 RXF8EN bit 0 Legend: R = Readable bit -n = Value at POR bit 7-0 Note 1: Note: C = Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘
PIC18F2682/2685/4682/4685 REGISTER 23-47: RXFBCONn: RECEIVE FILTER BUFFER CONTROL REGISTER n(1) RXFBCON0 R/W-0 F1BP_3 R/W-0 F1BP_2 R/W-0 F1BP_1 R/W-0 F1BP_0 R/W-0 F0BP_3 R/W-0 F0BP_2 R/W-0 F0BP_1 R/W-0 F0BP_0 RXFBCON1 R/W-0 F3BP_3 R/W-0 F3BP_2 R/W-0 F3BP_1 R/W-1 F3BP_0 R/W-0 F2BP_3 R/W-0 F2BP_2 R/W-0 F2BP_1 R/W-1 F2BP_0 RXFBCON2 R/W-0 F5BP_3 R/W-0 F5BP_2 R/W-0 F5BP_1 R/W-1 F5BP_0 R/W-0 F4BP_3 R/W-0 F4BP_2 R/W-0 F4BP_1 R/W-1 F4BP_0 RXFBCON3 R/W-0 F7BP_3 R/W-0 F7BP_2 R/W-0 F7BP_1
PIC18F2682/2685/4682/4685 REGISTER 23-48: MSEL0: MASK SELECT REGISTER 0(1) R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 FIL3_1 FIL3_0 FIL2_1 FIL2_0 FIL1_1 FIL1_0 FIL0_1 FIL0_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 FIL3_1:FIL3_0: Filter 3 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL2_1:FIL2_0: Filter 2 Sel
PIC18F2682/2685/4682/4685 REGISTER 23-49: MSEL1: MASK SELECT REGISTER 1(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 FIL7_1 FIL7_0 FIL6_1 FIL6_0 FIL5_1 FIL5_0 FIL4_1 FIL4_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 FIL7_1:FIL7_0: Filter 7 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL6_1:FIL6_0: Filter 6 Sel
PIC18F2682/2685/4682/4685 REGISTER 23-50: MSEL2: MASK SELECT REGISTER 2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL11_1 FIL11_0 FIL10_1 FIL10_0 FIL9_1 FIL9_0 FIL8_1 FIL8_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 FIL11_1:FIL11_0: Filter 11 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL10_1:FIL10_0: Fil
PIC18F2682/2685/4682/4685 REGISTER 23-51: MSEL3: MASK SELECT REGISTER 3(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL15_1 FIL15_0 FIL14_1 FIL14_0 FIL13_1 FIL13_0 FIL12_1 FIL12_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 FIL15_1:FIL15_0: Filter 15 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL14_1:FIL14_0:
PIC18F2682/2685/4682/4685 23.2.4 CAN BAUD RATE REGISTERS This section describes the CAN Baud Rate registers. Note: These registers are Configuration mode only.
PIC18F2682/2685/4682/4685 REGISTER 23-53: BRGCON2: BAUD RATE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), which
PIC18F2682/2685/4682/4685 REGISTER 23-54: BRGCON3: BAUD RATE CONTROL REGISTER 3 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 WAKDIS WAKFIL — — — SEG2PH2(1) R/W-0 R/W-0 SEG2PH1(1) SEG2PH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WAKDIS: Wake-up Disable bit 1 = Disable CAN bus activity wake-up feature 0 = Enable CAN bus activity wake-up feature bit 6 WAKFIL: Selects CAN bus Line Filter f
PIC18F2682/2685/4682/4685 23.2.5 CAN MODULE I/O CONTROL REGISTER This register controls the operation of the CAN module’s I/O pins in relation to the rest of the microcontroller.
PIC18F2682/2685/4682/4685 23.2.6 CAN INTERRUPT REGISTERS Register 23-56 through Register 23-58 in this section are the same as described in Section 9.0 “Interrupts”. They are duplicated here for convenience.
PIC18F2682/2685/4682/4685 REGISTER 23-57: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 Mode 0 Mode 1 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXBnIE R/W-0 (1) R/W-0 (1) TXB1IE TXB0IE R/W-0 R/W-0 (1) TXB1IE (1) TXB0IE R/W-0 R/W-0 RXB1IE RXB0IE R/W-0 R/W-0 RXBnIE FIFOWMIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x
PIC18F2682/2685/4682/4685 REGISTER 23-58: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 Mode 0 Mode 1,2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP TXB1IP(1) TXB0IP(1) RXB1IP RXB0IP R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXBnIP TXB1IP(1) TXB0IP(1) RXBnIP FIFOWMIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit
PIC18F2682/2685/4682/4685 REGISTER 23-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER(1) U-0 U-0 — — U-0 — R/W-0 TXB2IE (2) R/W-0 (2) TXB1IE R/W-0 U-0 U-0 — — (2) TXB0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-2 TXB2IE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bit(2) 1 = Transmit buffer interrupt is enabled 0 = Transmit buffer i
PIC18F2682/2685/4682/4685 TABLE 23-1: Address(1) CAN CONTROLLER REGISTER MAP Name Address Name Address Name Address Name F7Fh SPBRGH(3) F7Eh BAUDCON(3) F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh RXM1EIDH F7Dh —(4) F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch —(4) F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh —(4) F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah (4) — F5Fh CANCON_RO0 F3Fh CANCON_RO2 F1Fh RXM1EIDL F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F79h ECCP1DEL(3) F59h R
PIC18F2682/2685/4682/4685 TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name EFFh —(4) Address Name EDFh —(4) EFEh (4) — EFDh —(4) EFCh (4) Address Name Address Name EBFh —(4) E9Fh —(4) EDEh (4) — EBEh (4) — E9Eh —(4) EDDh —(4) EBDh —(4) E9Dh —(4) — EDCh — (4) EBCh (4) — E9Ch —(4) EFBh —(4) EDBh —(4) EBBh —(4) E9Bh —(4) EFAh (4) — EDAh (4) — EBAh (4) — E9Ah —(4) EF9h —(4) ED9h —(4) EB9h —(4) E99h —(4) EF8h (4) — E
PIC18F2682/2685/4682/4685 TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name Address Name Address Name Address Name E7Fh CANCON_RO4(2) E5Fh CANCON_RO6(2) E3Fh CANCON_RO8(2) E1Fh —(4) (2) (2) (2) E7Eh CANSTAT_RO4 E5Eh CANSTAT_RO6 E3Eh CANSTAT_RO8 E1Eh —(4) E7Dh B5D7 E5Dh B3D7 E3Dh B1D7 E1Dh —(4) E7Ch B5D6 E5Ch B3D6 E3Ch B1D6 E1Ch —(4) E7Bh B5D5 E5Bh B3D5 E3Bh B1D5 E1Bh —(4) E7Ah B5D4 E5Ah B3D4 E3Ah B1D4 E1Ah —(4) E79h B5D3 E59h B3D3
PIC18F2682/2685/4682/4685 TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name DFFh —(4) Address Name DDFh —(4) DFEh (4) — DFDh —(4) Address Name Address Name DBFh —(4) D9Fh —(4) DDEh — (4) DBEh (4) — D9Eh —(4) DDDh —(4) DBDh —(4) D9Dh —(4) (4) DBCh (4) — D9Ch —(4) DFCh TXBIE DDCh — DFBh —(4) DDBh —(4) DBBh —(4) D9Bh —(4) (4) DBAh (4) — D9Ah —(4) DB9h —(4) D99h —(4) (4) DFAh BIE0 DDAh — DF9h —(4) DD9h —(4) DF8h BSEL0
PIC18F2682/2685/4682/4685 TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name D7Fh —(4) D7Eh —(4) D7Dh —(4) D7Ch —(4) D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH D71h RXF9SIDL D70h RXF9SIDH D6Fh —(4) D6Eh —(4) D6Dh —(4) D6Ch —(4) D6Bh RXF8EIDL D6Ah RXF8EIDH D69h RXF8SIDL D68h RXF8SIDH D67h RXF7EIDL D66h RXF7EIDH D65h RXF7SIDL D64h
PIC18F2682/2685/4682/4685 23.3 CAN Modes of Operation The PIC18F2682/2685/4682/4685 has six main modes of operation: • • • • • • Configuration mode Disable mode Normal Operation mode Listen Only mode Loopback mode Error Recognition mode All modes, except Error Recognition, are requested by setting the REQOP bits (CANCON<7:5>). Error Recognition mode is requested through the RXM bits of the Receive Buffer register(s). Entry into a mode is Acknowledged by monitoring the OPMODE bits.
PIC18F2682/2685/4682/4685 23.3.4 LISTEN ONLY MODE Listen Only mode provides a means for the PIC18F2682/2685/4682/4685 devices to receive all messages, including messages with errors. This mode can be used for bus monitor applications or for detecting the baud rate in ‘hot plugging’ situations. For Auto-Baud Detection, it is necessary that there are at least two other nodes which are communicating with each other.
PIC18F2682/2685/4682/4685 23.4.3 MODE 2 – ENHANCED FIFO MODE In Mode 2, two or more receive buffers are used to form the receive FIFO (first in, first out) buffer. There is no one-to-one relationship between the receive buffer and acceptance filter registers. Any filter that is enabled and linked to any FIFO receive buffer can generate acceptance and cause FIFO to be updated. FIFO length is user programmable, from 2-8 buffers deep.
PIC18F2682/2685/4682/4685 23.5.4 PROGRAMMABLE AUTO-RTR BUFFERS In Mode 1 and 2, any of six programmable transmit/ receive buffers may be programmed to automatically respond to predefined RTR messages without user firmware intervention. Automatic RTR handling is enabled by setting the TXnEN bit in the BSEL0 register and the RTREN bit in the BnCON register.
PIC18F2682/2685/4682/4685 TRANSMIT PRIORITY buffer with the highest priority will be sent first. If two buffers have the same priority setting, the buffer with the highest buffer number will be sent first. There are four levels of transmit priority. If TXP bits for a particular message buffer are set to ‘11’, that buffer has the highest possible priority. If TXP bits for a particular message buffer are set to ‘00’, that buffer has the lowest possible priority.
PIC18F2682/2685/4682/4685 23.7 23.7.1 Message Reception RECEIVING A MESSAGE Of all receive buffers, the MAB is always committed to receiving the next message from the bus. The MCU can access one buffer while the other buffer is available for message reception or holding a previously received message. Note: The entire contents of the MAB are moved into the receive buffer once a message is accepted.
PIC18F2682/2685/4682/4685 23.7.3 ENHANCED FIFO MODE When configured for Mode 2, two of the dedicated receive buffers in combination with one or more programmable transmit/receive buffers, are used to create a maximum of an 8-buffer deep FIFO buffer. In this mode, there is no direct correlation between filters and receive buffer registers. Any filter that has been enabled can generate an acceptance.
PIC18F2682/2685/4682/4685 In Mode 1 and 2, there are an additional 10 acceptance filters, RXF6-RXF15, creating a total of 16 available filters. RXF15 can be used either as an acceptance filter or acceptance mask register. Each of these acceptance filters can be individually enabled or disabled by setting or clearing the RXFENn bit in the RXFCONn register. Any of these 16 acceptance filters can be dynamically associated with any of the receive buffers.
PIC18F2682/2685/4682/4685 23.9 Baud Rate Setting The Nominal Bit Time can be thought of as being divided into separate, non-overlapping time segments. These segments (Figure 23-4) include: All nodes on a given CAN bus must have the same nominal bit rate. The CAN protocol uses Non-Returnto-Zero (NRZ) coding which does not encode a clock within the data stream. Therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitter’s clock.
PIC18F2682/2685/4682/4685 23.9.1 EXTERNAL CLOCK, INTERNAL CLOCK AND MEASURABLE JITTER IN HSPLL-BASED OSCILLATORS The microcontroller clock frequency generated from a PLL circuit is subject to a jitter, also defined as Phase Jitter or Phase Skew. For its PIC18 Enhanced microcontrollers, Microchip specifies phase jitter (Pjitter) as being 2% (Gaussian distribution, within 3 standard deviations, see parameter F13 in Table 27-7) and Total Jitter (Tjitter) as being 2 * Pjitter.
PIC18F2682/2685/4682/4685 Table 23-3 shows the relation between the clock generated by the PLL and the frequency error from jitter (measured jitter-induced error of 2%, Gaussian distribution, within 3 standard deviations), as a percentage of the nominal clock frequency. TABLE 23-3: PLL Output This is clearly smaller than the expected drift of a crystal oscillator, typically specified at 100 ppm or 0.01%. If we add jitter to oscillator drift, we have a total frequency drift of 0.0132%.
PIC18F2682/2685/4682/4685 23.9.2 TIME QUANTA 23.9.3 SYNCHRONIZATION SEGMENT As already mentioned, the Time Quanta is a fixed unit derived from the oscillator period and baud rate prescaler. Its relationship to TBIT and the Nominal Bit Rate is shown in Example 23-6. This part of the bit time is used to synchronize the various CAN nodes on the bus. The edge of the input signal is expected to occur during the sync segment. The duration is 1 TQ. EXAMPLE 23-6: 23.9.
PIC18F2682/2685/4682/4685 23.10 Synchronization To compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (Sync_Seg). The circuit will then adjust the values of Phase Segment 1 and Phase Segment 2 as necessary.
PIC18F2682/2685/4682/4685 FIGURE 23-7: Sync SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2) Prop Segment Phase Segment 1 TQ Phase Segment 2 ≤ SJW Sample Point Actual Bit Length Nominal Bit Length 23.11 Programming Time Segments Some requirements for programming of the time segments: • Prop_Seg + Phase_Seg 1 ≥ Phase_Seg 2 • Phase_Seg 2 ≥ Sync Jump Width. For example, assume that a 125 kHz CAN baud rate is desired, using 20 MHz for FOSC.
PIC18F2682/2685/4682/4685 23.14 Error Detection 23.14.6 The CAN protocol provides sophisticated error detection mechanisms. The following errors can be detected. Detected errors are made public to all other nodes via error frames. The transmission of the erroneous message is aborted and the frame is repeated as soon as possible. Furthermore, each CAN node is in one of the three error states: “error-active”, “error-passive” or “bus-off”, according to the value of the internal error counters.
PIC18F2682/2685/4682/4685 FIGURE 23-8: ERROR MODES STATE DIAGRAM Reset ErrorActive RXERRCNT < 127 or TXERRCNT < 127 RXERRCNT > 127 or TXERRCNT > 127 128 occurrences of 11 consecutive “recessive” bits ErrorPassive TXERRCNT > 255 BusOff 23.15 CAN Interrupts The module has several sources of interrupts. Each of these interrupts can be individually enabled or disabled. The PIR3 register contains interrupt flags. The PIE3 register contains the enables for the 8 main interrupts.
PIC18F2682/2685/4682/4685 23.15.1 INTERRUPT CODE BITS To simplify the interrupt handling process in user firmware, the ECAN module encodes a special set of bits. In Mode 0, these bits are ICODE<3:1> in the CANSTAT register. In Mode 1 and 2, these bits are EICODE<4:0> in the CANSTAT register. Interrupts are internally prioritized such that the higher priority interrupts are assigned lower values.
PIC18F2682/2685/4682/4685 23.15.5 BUS ACTIVITY WAKE-UP INTERRUPT When the PIC18F2682/2685/4682/4685 devices are in Sleep mode and the bus activity wake-up interrupt is enabled, an interrupt will be generated and the WAKIF bit will be set when activity is detected on the CAN bus. This interrupt causes the PIC18F2682/2685/4682/ 4685 devices to exit Sleep mode. The interrupt is reset by the MCU, clearing the WAKIF bit. 23.15.
PIC18F2682/2685/4682/4685 24.0 SPECIAL FEATURES OF THE CPU The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays.
PIC18F2682/2685/4682/4685 REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabl
PIC18F2682/2685/4682/4685 REGISTER 24-2: U-0 CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 — — U-0 — R/P-1 BORV1 R/P-1 BORV0 R/P-1 R/P-1 (1) BOREN1 BOREN0 bit 7 R/P-1 (1) PWRTEN(1) bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits 11 = Minimum setting . . .
PIC18F2682/2685/4682/4685 REGISTER 24-3: U-0 CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 — — U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 =
PIC18F2682/2685/4682/4685 REGISTER 24-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 U-0 MCLRE — — — — LPT1OSC PBADEN — bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6-3 Unimplemented: Re
PIC18F2682/2685/4682/4685 REGISTER 24-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 — — CP5(1) CP4 CP3 CP2 CP1 CP0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-6 Unimplemented: Read as ‘0’ bit 5 CP5: Code Protection bit(1) 1 = Block 5 (014000-017FFFh) not code-protected 0 = Block 5 (014000-017F
PIC18F2682/2685/4682/4685 REGISTER 24-8: U-0 CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 — — R/C-1 (1) WRT5 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 WRT4 WRT3 WRT2 WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-6 Unimplemented: Read as ‘0’ bit 5 WRT5: Write Protection bit(1) 1 = Block 5 (014000-017FFFh) not write-protected 0 = Block 5 (0140
PIC18F2682/2685/4682/4685 REGISTER 24-9: R/C-1 CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 WRTD WRTB R-1 (1) WRTC U-0 U-0 U-0 U-0 U-0 — — — — — bit 7 bit 0 Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection
PIC18F2682/2685/4682/4685 REGISTER 24-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 — — EBTR5(1) EBTR4 EBTR3 EBTR2 EBTR1 EBTR0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-6 Unimplemented: Read as ‘0’ bit 5 EBTR5: Table Read Protection bit(1) 1 = Block 5 (014000-017FFFh) not protected from table
PIC18F2682/2685/4682/4685 REGISTER 24-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2682/2685/4682/4685 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F2682 001 = PIC18F2685 010 = PIC18F4682 011 = PIC18F4685 bit 4-0 REV3:REV0: Revision ID bits These bits are used to
PIC18F2682/2685/4682/4685 24.2 Watchdog Timer (WDT) For PIC18F2682/2685/4682/4685 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.
PIC18F2682/2685/4682/4685 REGISTER 24-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configurati
PIC18F2682/2685/4682/4685 24.3 Two-Speed Start-up Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF2:IRCF0 bits prior to entering Sleep mode. The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO Configuration bit.
PIC18F2682/2685/4682/4685 24.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure.
PIC18F2682/2685/4682/4685 FIGURE 24-4: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 24.4.3 CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register.
PIC18F2682/2685/4682/4685 24.5 Program Verification and Code Protection Each of the five blocks has three code protection bits associated with them. They are: The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC devices. • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. One of these is a boot block of 2 Kbytes.
PIC18F2682/2685/4682/4685 TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — CP5(1) CP4 CP3 CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — WRT4 WRT3 WRT2 WRT1 WRT0 — — — — — EBTR4 EBTR3 EBTR2 EBTR1 EBTR0 — — — — — 30000Ah CONFIG6L — — 30000Bh CONFIG6H WRTD WRTB 30000Ch CONFIG7L — — 30000Dh CONFIG7H — EBTRB WRT5 (1) WRTC EBTR5 — (1) Legend: Shaded cells are uni
PIC18F2682/2685/4682/4685 FIGURE 24-6: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 0008FFh PC = 003FFEh WRTB, EBTRB = 11 WRT0, EBTR0 = 01 TBLWT* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h PC = 00BFFEh WRT2, EBTR2 = 11 TBLWT* 00BFFFh 00C000h 00FFFFh 010000h WRT3, EBTR3 = 11 WRT4, EBTR3 = 11 013FFFh 014000h WRT5, EBTR3 = 11 017FFFh Results: All table writes disabled to Blockn whenever WRTn = 0.
PIC18F2682/2685/4682/4685 FIGURE 24-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 0008FFh PC = 003FFEh WRTB, EBTRB = 11 WRT0, EBTR0 = 01 TBLRD* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h 00FFFFh 010000h WRT3, EBTR3 = 11 WRT4, EBTR3 = 11 013FFFh 014000h WRT5, EBTR3 = 11 017FFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0.
PIC18F2682/2685/4682/4685 24.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 24.5.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected.
PIC18F2682/2685/4682/4685 25.0 INSTRUCTION SET SUMMARY PIC18F2682/2685/4682/4685 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions, for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 25.
PIC18F2682/2685/4682/4685 TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18F2682/2685/4682/4685 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a ADDWF MYREG, W, B f (FILE #) d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destinatio
PIC18F2682/2685/4682/4685 TABLE 25-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Bits Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f,
PIC18F2682/2685/4682/4685 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Bits Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None
PIC18F2682/2685/4682/4685 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Bits Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG
PIC18F2682/2685/4682/4685 25.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) + (f) → dest Status Affected: N, OV, C, DC, Z k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F2682/2685/4682/4685 ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Operation: (W) + (f) + (C) → dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F2682/2685/4682/4685 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None f {,d {,a}} Operation: (W) .AND. (f) → dest Status Affected: N, Z Encoding: 0001 Description: Encoding: 01da ffff ffff 1110 Description: The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18F2682/2685/4682/4685 BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Negative bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None f, b {,a} Operation: 0 → f Status Affected: None Encoding: 1001 Description: Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F2682/2685/4682/4685 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’ (PC) + 2 + 2n → PC Operation: if Negative bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0011 nnnn nnnn If the Carry bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F2682/2685/4682/4685 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’ (PC) + 2 + 2n → PC Operation: if Zero bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is ‘0’, then the program will branch.
PIC18F2682/2685/4682/4685 BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: -1024 ≤ n ≤ 1023 Operands: Operation: (PC) + 2 + 2n → PC Status Affected: None 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 1 → f Status Affected: None Encoding: n 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n.
PIC18F2682/2685/4682/4685 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18F2682/2685/4682/4685 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Operation: (f) → f Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in data memory location ‘f’ is inverted. 0100 nnnn nnnn If the Overflow bit is ‘1’, then the program will branch.
PIC18F2682/2685/4682/4685 BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 ≤ n ≤ 127 Operands: Operation: if Zero bit is ‘1’ (PC) + 2 + 2n → PC 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: Status Affected: None (PC) + 4 → TOS, k → PC<20:1>; if s = 1, (W) → WS, (STATUS) → STATUSS, (BSR) → BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F2682/2685/4682/4685 CLRF Clear f Syntax: CLRF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] f {,a} Operation: 000h → f 1→Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register.
PIC18F2682/2685/4682/4685 COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: Operation: (f) → dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘1’, the result is stored in W.
PIC18F2682/2685/4682/4685 CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) − (W), skip if (f) > (W) (unsigned comparison) Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of t
PIC18F2682/2685/4682/4685 DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> >9] or [DC = 1] then (W<3:0>) + 6 → W<3:0>; else (W<3:0>) → W<3:0> 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> >9] or [C = 1] then (W<7:4>) + 6 → W<7:4>; C = 1; else (W<7:4>) → W<7:4> Status Affected: 0000 Description: C Encoding: 0000 0000 0000 DAW adjusts th
PIC18F2682/2685/4682/4685 DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F2682/2685/4682/4685 GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 ≤ k ≤ 1048575 Operands: Operation: k → PC<20:1> Status Affected: None 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 1110 1111 2nd word(k<19:8>) Description: 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
PIC18F2682/2685/4682/4685 INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Increment f, Skip if Not 0 f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: Operation: (f) + 1 → dest, skip if result = 0 Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented.
PIC18F2682/2685/4682/4685 IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .OR. k → W Status Affected: N, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .OR. (f) → dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18F2682/2685/4682/4685 LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0≤f≤2 0 ≤ k ≤ 4095 Operands: Operation: k → FSRf 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: f → dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18F2682/2685/4682/4685 MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operands: 0 ≤ k ≤ 255 Operation: k → BSR None Operation: (fs) → fd Status Affected: Status Affected: None Encoding: Encoding: 1st word (source) 1100 1111 2nd word (destin.) Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F2682/2685/4682/4685 MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k→W 0 ≤ f ≤ 255 a ∈ [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18F2682/2685/4682/4685 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None k Operands: 0 ≤ k ≤ 255 Operation: (W) x k → PRODH:PRODL Status Affected: None Encoding: 0000 Description: 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
PIC18F2682/2685/4682/4685 NEGF Negate f NOP No Operation Syntax: NEGF Syntax: NOP Operands: 0 ≤ f ≤ 255 a ∈ [0,1] f {,a} Operands: None Operation: No operation None Operation: (f)+1→f Status Affected: Status Affected: N, OV, C, DC, Z Encoding: Encoding: 0110 Description: 110a ffff Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F2682/2685/4682/4685 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 Description: 0000 0000 0110 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F2682/2685/4682/4685 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, (PC) + 2 + 2n → PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18F2682/2685/4682/4685 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged Operation: k → W, (TOS) → PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: kkkk kkkk W is loaded
PIC18F2682/2685/4682/4685 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s ∈ [0,1] Operands: Operation: (TOS) → PC; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subrou
PIC18F2682/2685/4682/4685 RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → dest<0> Operation: Status Affected: N, Z (f) → dest, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
PIC18F2682/2685/4682/4685 RRNCF Rotate Right f (No Carry) SETF Syntax: RRNCF Syntax: SETF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: FFh → f Operation: (f) → dest, (f<0>) → dest<7> Status Affected: None Status Affected: Encoding: N, Z Encoding: 0100 Description: f {,d {,a}} 00da Set f ffff ffff 0110 Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F2682/2685/4682/4685 SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 0101 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
PIC18F2682/2685/4682/4685 SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k – (W) → W Status Affected: N, OV, C, DC, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F2682/2685/4682/4685 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: (f<3:0>) → dest<7:4>, Status Affected: N, OV, C, DC, Z Encoding: 0101 Description: f {,d {,a}} 10da (f<7:4>) → dest<3:0> ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
PIC18F2682/2685/4682/4685 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT, TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) + 1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) – 1 → TBLPTR; if TBLRD +*, (TBLPTR) + 1 → TBLPTR, (Prog Mem (TBLPTR)) → TABLAT Status Affected: None Encoding: Description: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +* B
PIC18F2682/2685/4682/4685 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) → Holding Register, TBLPTR – No Change; if TBLWT*+, (TABLAT) → Holding Register, (TBLPTR) + 1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register, (TBLPTR) – 1 → TBLPTR; if TBLWT+*, (TBLPTR) + 1 → TBLPTR, (TABLAT) → Holding Register Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructi
PIC18F2682/2685/4682/4685 TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → W N, Z Operation: skip if f = 0 Status Affected: Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18F2682/2685/4682/4685 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
PIC18F2682/2685/4682/4685 25.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 25-3. Detailed descriptions are provided in Section 25.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 25-1 apply to both the standard and extended PIC18 instruction sets. In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F2682/2685/4682/4685 devices also provide an optional extension to the core CPU functionality.
PIC18F2682/2685/4682/4685 25.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operands: 0 ≤ k ≤ 63 FSR(f) + k → FSR(f) Operation: Operation: FSR2 + k → FSR2, PC = (TOS) Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18F2682/2685/4682/4685 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) → TOS, (W) → PCL, (PCLATH) → PCH, (PCLATU) → PCU 0 ≤ zs ≤ 127 0 ≤ fd ≤ 4095 Operation: ((FSR2) + zs) → fd Status Affected: None Status Affected: 0000 Description Encoding: None Encoding: 0000 Move Indexed to f 0001 0100 First, the return address (PC + 2) is pushed onto the return stack.
PIC18F2682/2685/4682/4685 MOVSS Move Indexed to Indexed PUSHL Syntax: Syntax: PUSHL k Operands: MOVSS [zs], [zd] 0 ≤ zs ≤ 127 0 ≤ zd ≤ 127 Operands: 0 ≤ k ≤ 255 Operation: ((FSR2) + zs) → ((FSR2) + zd) Operation: k → (FSR2), FSR2 – 1 → FSR2 Status Affected: None Status Affected: None Encoding: 1st word (source) 1110 1111 2nd word (dest.) Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register.
PIC18F2682/2685/4682/4685 SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operands: 0 ≤ k ≤ 63 Operation: Operation: FSRf – k → FSRf FSR2 – k → FSR2, (TOS) → PC Status Affected: None Encoding: 1110 Subtract Literal from FSR2 and Return Status Affected: None 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18F2682/2685/4682/4685 25.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 5.6.1 “Indexed Addressing with Literal Offset”).
PIC18F2682/2685/4682/4685 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 d ∈ [0,1] a=0 Operands: 0 ≤ f ≤ 95 0≤b≤7 a=0 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2 + k)) Status Affected: None [k] {,d} Status Affected: N, OV, C, DC, Z Encoding: 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offse
PIC18F2682/2685/4682/4685 25.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18F2682/2685/4682/4685 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18F2682/2685/4682/4685 26.
PIC18F2682/2685/4682/4685 26.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
PIC18F2682/2685/4682/4685 26.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18F2682/2685/4682/4685 26.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 26.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC18F2682/2685/4682/4685 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) ............................................
PIC18F2682/2685/4682/4685 FIGURE 27-1: PIC18F2682/2685/4682/4685 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18F268X/468X 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 27-2: PIC18LF2682/2685/4682/4685 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LF268X/468X 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.
PIC18F2682/2685/4682/4685 27.1 DC Characteristics: Supply Voltage PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2682/2685/4682/4685 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F2682/2685/4682/4685 27.
PIC18F2682/2685/4682/4685 27.
PIC18F2682/2685/4682/4685 27.
PIC18F2682/2685/4682/4685 27.
PIC18F2682/2685/4682/4685 27.
PIC18F2682/2685/4682/4685 27.
PIC18F2682/2685/4682/4685 27.
PIC18F2682/2685/4682/4685 27.
PIC18F2682/2685/4682/4685 27.3 DC Characteristics: PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V ≤ VDD ≤ 5.5V Input Low Voltage I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer VSS 0.
PIC18F2682/2685/4682/4685 27.3 DC Characteristics: PIC18F2682/2685/4682/4685 (Industrial) PIC18LF2682/2685/4682/4685 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param Symbol No. VOL Characteristic Min Max Units Conditions Output Low Voltage D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D083 OSC2/CLKO (RC, RCIO, EC, ECIO modes) — 0.6 V IOL = 1.6 mA, VDD = 4.
PIC18F2682/2685/4682/4685 TABLE 27-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC Characteristics Param No. Sym Characteristic Min Typ† Max Units Conditions 9.00 — 13.
PIC18F2682/2685/4682/4685 TABLE 27-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated). Param No. Sym Characteristics Min Typ Max Units Comments D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage* 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio* 55 — — dB 300 TRESP Response Time(1)* — 150 400 ns PIC18FXXXX — 150 600 ns PIC18LFXXXX, VDD = 2.
PIC18F2682/2685/4682/4685 FIGURE 27-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD (HLVDIF can be cleared in software) VLVD (HLVDIF set by hardware) HLVDIF TABLE 27-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym No. D420 Characteristic HLVD Voltage on VDD Transition High-to-Low Min Typ† Max Units HLVDL<3:0> = 0000 2.12 2.17 2.22 V HLVDL<3:0> = 0001 2.18 2.23 2.
PIC18F2682/2685/4682/4685 27.4 27.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2.
PIC18F2682/2685/4682/4685 27.4.2 TIMING CONDITIONS Note: The temperature and voltages specified in Table 27-5 apply to all timing specifications unless otherwise noted. Figure 27-4 specifies the load conditions for the timing specifications. TABLE 27-5: Because of space limitations, the generic terms “PIC18FXXXX” and “PIC18LFXXXX” are used throughout this section to refer to the PIC18F2682/2685/4682/4685 and PIC18LF2682/2685/4682/4685 families of devices specifically and only those devices.
PIC18F2682/2685/4682/4685 27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 27-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min External CLKI Frequency(1) DC 1 MHz XT, RC Oscillator modes DC 25 MHz HS Oscillator mode DC 31.25 kHz LP Oscillator mode DC 40 MHz EC Oscillator mode DC 4 MHz RC Oscillator mode 0.
PIC18F2682/2685/4682/4685 TABLE 27-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Sym Characteristic Min Typ† Max 4 16 — — 10 40 Units F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 trc PLL Start-up Time (Lock Time) — — 2 ms ΔCLK CLKO Stability (Jitter) -2 — +2 % F13 Conditions MHz HS mode only MHz HS mode only † Data in “Typ” column is at 5V, 25°C unless otherwise stated.
PIC18F2682/2685/4682/4685 FIGURE 27-6: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 27-4 for load conditions. TABLE 27-9: Param No.
PIC18F2682/2685/4682/4685 FIGURE 27-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 27-4 for load conditions. FIGURE 27-8: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.
PIC18F2682/2685/4682/4685 FIGURE 27-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 27-4 for load conditions. TABLE 27-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PIC18F2682/2685/4682/4685 FIGURE 27-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 27-4 for load conditions. TABLE 27-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param No.
PIC18F2682/2685/4682/4685 FIGURE 27-11: PARALLEL SLAVE PORT TIMING (PIC18F4682/4685) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 27-4 for load conditions. TABLE 27-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4682/4685) Param. No.
PIC18F2682/2685/4682/4685 FIGURE 27-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 27-4 for load conditions. TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PIC18F2682/2685/4682/4685 FIGURE 27-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO LSb bit 6 - - - - - -1 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure 27-4 for load conditions. TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC18F2682/2685/4682/4685 FIGURE 27-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 77 75, 76 MSb In SDI 73 Note: bit 6 - - - -1 LSb In 74 Refer to Figure 27-4 for load conditions. TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No.
PIC18F2682/2685/4682/4685 FIGURE 27-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI MSb In 77 LSb In bit 6 - - - -1 74 Note: Refer to Figure 27-4 for load conditions. TABLE 27-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PIC18F2682/2685/4682/4685 I2C™ BUS START/STOP BITS TIMING FIGURE 27-16: SCL 91 93 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-4 for load conditions. TABLE 27-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18F2682/2685/4682/4685 TABLE 27-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR 103 TF TSU:STA 90 91 THD:STA THD:DAT 106 107 TSU:DAT TSU:STO 92 109 TAA 110 TBUF D102 CB Note 1: 2: Characteristic Clock High Time Clock Low Time Min Max Units Conditions 100 kHz mode 4.0 — μs PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs PIC18FXXXX must operate at a minimum of 10 MHz MSSP module 1.5 TCY — 100 kHz mode 4.
PIC18F2682/2685/4682/4685 MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS FIGURE 27-18: SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-4 for load conditions. TABLE 27-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18F2682/2685/4682/4685 TABLE 27-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) Clock High Time 2(TOSC)(BRG + 1) — ms 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.
PIC18F2682/2685/4682/4685 FIGURE 27-20: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 Note: 122 Refer to Figure 27-4 for load conditions. TABLE 27-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18F2682/2685/4682/4685 TABLE 27-24: A/D CONVERTER CHARACTERISTICS: PIC18F2682/2685/4682/4685 (INDUSTRIAL) PIC18LF2682/2685/4682/4685 (INDUSTRIAL) Param No. Sym Characteristic Min Typ Max Units bit Conditions ΔVREF ≥ 3.0V A01 NR Resolution — — 10 A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±1 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.
PIC18F2682/2685/4682/4685 FIGURE 27-22: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 132 A/D CLK(1) 9 A/D DATA 8 ... ... 7 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PIC18F2682/2685/4682/4685 28.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and tables are not available at this time. © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 456 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example PIC18F2685-I/SP e3 0710017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...
PIC18F2682/2685/4682/4685 29.1 Package Marking Information (Continued) 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS39761C-page 458 Example PIC18F4685 -I/PT e3 0710017 Example PIC18F4685 -I/ML e3 0710017 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 29.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A – – .
PIC18F2682/2685/4682/4685 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e b h α A2 A h c φ L A1 Units Dimension Limits Number of Pins β L1 MILLMETERS MIN N NOM MAX 28 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.
PIC18F2682/2685/4682/4685 40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 40 Pitch e Top to Seating Plane A – – .250 Molded Package Thickness A2 .125 – .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .
PIC18F2682/2685/4682/4685 44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 44 Lead Pitch e Overall Height A – 0.80 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.
PIC18F2682/2685/4682/4685 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 44 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 464 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 APPENDIX A: REVISION HISTORY Revision A (February 2006) Original data sheet for PIC18F2682/2685/4682/4685 devices. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (January 2007) Major edits to Section 27.0 “Electrical Characteristics”. Packaging diagrams have been updated and minor edits to text have been made throughout document. Revision C (October 2009) Updated to remove Preliminary status.
PIC18F2682/2685/4682/4685 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B.
PIC18F2682/2685/4682/4685 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442.” The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations.
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 468 © 2009 Microchip Technology Inc.
PIC18F2682/2685/4682/4685 INDEX A A/D ................................................................................... 249 Acquisition Requirements ........................................ 254 ADCON0 Register .................................................... 249 ADCON1 Register .................................................... 249 ADCON2 Register .................................................... 249 ADRESH Register ............................................ 249, 252 ADRESL Register ...........
PIC18F2682/2685/4682/4685 Capture (CCP1 Module) ................................................... 167 Associated Registers ............................................... 170 CAN Message Time-Stamp ..................................... 167 CCP1 Pin Configuration ........................................... 167 CCPR1H:CCPR1L Registers ................................... 167 Prescaler .................................................................. 167 Software Interrupt ...................................
PIC18F2682/2685/4682/4685 Data EEPROM Memory ................................................... 107 Associated Registers ............................................... 111 EEADR and EEADRH Registers ............................. 107 EECON1 and EECON2 Registers ........................... 107 Operation During Code-Protect ............................... 110 Protection Against Spurious Write ........................... 110 Reading ....................................................................
PIC18F2682/2685/4682/4685 Enhanced Capture/Compare/PWM (ECCP1) .................. 175 Associated Registers ............................................... 188 Capture and Compare Modes .................................. 176 Capture Mode. See Capture (ECCP1 Module). Outputs and Configuration ....................................... 176 Pin Configurations for ECCP1 ................................. 176 PWM Mode. See PWM (ECCP1 Module). Standard PWM Mode ...............................................
PIC18F2682/2685/4682/4685 Master Mode ............................................................ 213 Operation ......................................................... 214 Reception ......................................................... 219 Repeated Start Condition Timing ..................... 218 Start Condition ................................................. 217 Transmission ................................................... 219 Transmit Sequence ..........................................
PIC18F2682/2685/4682/4685 Interrupt Sources .............................................................. 345 A/D Conversion Complete ....................................... 253 Capture Complete (CCP1) ....................................... 167 Compare Complete (CCP1) ..................................... 169 ECAN Module .......................................................... 342 Interrupt-on-Change (RB7:RB4) .............................. 134 INTx Pin ..................................................
PIC18F2682/2685/4682/4685 RD0/PSP0/C1IN+ ...................................................... 22 RD1/PSP1/C1IN- ....................................................... 22 RD2/PSP2/C2IN+ ...................................................... 22 RD3/PSP3/C2IN- ....................................................... 22 RD4/PSP4/ECCP1/P1A ............................................. 22 RD5/PSP5/P1B .......................................................... 22 RD6/PSP6/P1C ....................................
PIC18F2682/2685/4682/4685 PWM (ECCP1 Module) .................................................... 177 Auto-Shutdown ........................................................ 172 Direction Change in Full-Bridge Output Mode .................................................... 182 Duty Cycle ................................................................ 178 ECCPR1H:ECCPR1L Registers .............................. 177 Effects of a Reset ..................................................... 187 Enhanced Mode ..
PIC18F2682/2685/4682/4685 RXBnEIDL (Receive Buffer n Extended Identifier, Low Byte) ......................... 294 RXBnSIDH (Receive Buffer n Standard Identifier, High Byte) ......................... 293 RXBnSIDL (Receive Buffer n Standard Identifier, Low Byte) ......................... 294 RXERRCNT (Receive Error Count) ......................... 296 RXFBCONn (Receive Filter Buffer Control n) .......... 309 RXFCONn (Receive Filter Control n) .......................
PIC18F2682/2685/4682/4685 T T0CON Register PSA Bit ..................................................................... 151 T0CS Bit ................................................................... 150 T0PS2:T0PS0 Bits ................................................... 151 T0SE Bit ................................................................... 150 Table Reads/Table Writes .................................................. 66 TBLRD ...................................................................
PIC18F2682/2685/4682/4685 SPI Mode (Slave Mode with CKE = 0) ..................... 196 SPI Mode (Slave Mode with CKE = 1) ..................... 196 Stop Condition Receive or Transmit Mode .............. 222 Synchronous Reception (Master Mode, SREN) ...... 246 Synchronous Transmission ...................................... 244 Synchronous Transmission (Through TXEN) .............................................. 245 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) ...................................
PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 480 © 2009 Microchip Technology Inc.
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PIC18F2682/2685/4682/4685 PIC18F2682/2685/4682/4685 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F2682/2685(1), PIC18F4682/4685(1), PIC18F2682/2685T(2), PIC18F4682/4685T(2); VDD range 4.2V to 5.5V PIC18LF2682/2685(1), PIC18LF4682/4685(1), PIC18LF2682/2685T(2), PIC18LF4682/4685T(2); VDD range 2.0V to 5.
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