Datasheet

PIC18F2525/2620/4525/4620
DS39626E-page 224 © 2008 Microchip Technology Inc.
REGISTER 19-2: ADCON1: A/D CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-q
(1)
R/W-q
(1)
R/W-q
(1)
— —
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 VCFG1: Voltage Reference Configuration bit (V
REF- source)
1 = V
REF- (AN2)
0 = V
SS
bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = V
DD
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
Note 1: The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When
PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111.
2: AN5 through AN7 are available only on 40/44-pin devices.
A = Analog input D = Digital I/O
PCFG3:
PCFG0
AN12 AN11 AN10 AN9 AN8 AN7
(2)
AN6
(2)
AN5
(2)
AN4 AN3 AN2 AN1 AN0
0000
(1)
AAAAAAAAAAAAA
0001 AAAAAAAAAAAAA
0010 AAAAAAAAAAAAA
0011 DA AAAAAAAAAAA
0100 DDAAAAAAAAAAA
0101 DDDAAAAAAAAAA
0110 DDDDAAAAAAAAA
0111
(1)
DDDDDAAAAAAAA
1000 D D DDDDAAAAAAA
1001 D D DDDDDAAAAAA
1010 D D DDDDDDAAAAA
1011 D D DDDDDDDAAAA
1100 D D DDDDDDDDAAA
1101 D D DDDDDDDDDAA
1110 D D DDDDDDDDDDA
1111 D D DDDDDDDDDDD