Datasheet

 2012 Microchip Technology Inc. DS30684A-page 71
PIC18(L)F2X/45K50
5.6 Low-Power BOR (LPBOR)
PIC18(L)F2X/45K50 devices implement a low-power
Brown-out Reset circuit (LPBOR
). The LPBOR is used
to monitor the external V
DD pin.
When low voltage is detected, the device is held in
Reset. When this occurs, the RCON<0> (BOR) bit is
changed to indicate that a BOR reset has occurred.
This is the same bit in the RCON register that is set for
the traditional BOR.
LPBOR
provides the user with a lower power BOR
option. In exchange for the lower power, the LPBOR
circuit trips at a loose voltage range compared to the
traditional BOR voltage trip point options.
LPBOR is enabled by the Configuration bit
CONFIG2L<6> (L
PBOR). The threshold of the LPBOR
is not configurable and its range is specified as
parameter D006.
5.7 Device Reset Timers
PIC18(L)F2X/45K50 devices incorporate three
separate on-chip timers that help regulate the Power-
on Reset process. Their main function is to ensure that
the device clock is stable before code is executed.
These timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
5.7.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of PIC18(L)F2X/45K50
devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32 s = 65.6 ms. While the
PWRT is counting, the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
5.7.2 OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or on exit from all
power-managed modes that stop the external oscillator.
5.7.3 PLL LOCK TIME-OUT
With the PLL enabled, the time-out sequence following a
Power-on Reset is slightly different from other oscillator
modes. A separate timer is used to provide a fixed time-
out that is sufficient for the PLL to lock to the main
oscillator frequency. This PLL lock time-out (T
PLL) is
typically 2 ms and follows the oscillator start-up time-out.
5.7.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).
2. Then, the OST is activated.
The total time-out will vary based on oscillator
configuration and the status of the PWRT. Figure 5-3,
Figure 5-4, Figure 5-5, Figure 5-6 and Figure 5-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 5-3 through 5-6 also
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, on
the other hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire, after
which, bringing MCLR
high will allow program
execution to begin immediately (Figure 5-5). This is
useful for testing purposes or to synchronize more than
one PIC
®
MCU device operating in parallel.
TABLE 5-1: BOR CONFIGURATIONS
BOR Configuration Status of
SBOREN
(RCON<6>)
BOR Operation
BOREN1 BOREN0
00Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.
01Available BOR enabled by software; operation controlled by SBOREN.
10Unavailable BOR enabled by hardware in Run and Idle modes, disabled during
Sleep mode.
11Unavailable BOR enabled by hardware; must be disabled by reprogramming the Configuration bits.