Datasheet

 2012 Microchip Technology Inc. DS30684A-page 61
PIC18(L)F2X/45K50
4.4.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the SOSC
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS<1:0> bits to ‘01’ and execute
SLEEP. When the clock source is switched to the SOSC
oscillator, the primary oscillator is shut down, the OSTS
bit is cleared and the SOSCRUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the SOSC oscillator. After an interval
of T
CSD following the wake event, the CPU begins exe-
cuting code being clocked by the SOSC oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the SOSC oscillator continues to run (see Figure 4-7).
FIGURE 4-6: TRANSITION TIMING FOR ENTRY TO IDLE MODE
FIGURE 4-7: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Note: The SOSC oscillator should already be
running prior to entering SEC_IDLE
mode. At least one of the secondary oscil-
lator enable bits (SOSCEN, T1CON<3> or
T3CON<3>) must be set when the SLEEP
instruction is executed. Otherwise, the
main system clock will continue to operate
in the previously selected mode and the
corresponding IDLE mode will be entered
(i.e., PRI_IDLE or RC_IDLE).
Q1
Peripheral
Program
PC PC + 2
OSC1
Q3
Q4
Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program
PC
CPU Clock
Q1 Q3 Q4
Clock
Counter
Q2
Wake Event
TCSD