Datasheet

 2012 Microchip Technology Inc. DS30684A-page 529
PIC18(L)F2X/45K50
Top-of-Stack Access........................................................... 78
TSTFSZ ............................................................................ 445
Two-Speed Clock Start-up Mode ........................................ 45
Two-Speed Start-up .......................................................... 385
Two-Word Instructions
Example Cases........................................................... 83
TXREG.............................................................................. 271
TXSTA Register ................................................................ 279
BRGH Bit .................................................................. 282
U
Universal Serial Bus
Address Register (UADDR) ...................................... 359
Associated Registers ................................................ 376
Buffer Descriptor Table............................................. 360
Buffer Descriptors ..................................................... 360
Address Validation............................................ 363
Assignment in Different Buffering Modes ......... 365
BDnSTAT Register (CPU Mode) ...................... 361
BDnSTAT Register (SIE Mode) ........................ 363
Byte Count ........................................................ 363
Example............................................................ 360
Memory Map..................................................... 364
Ownership......................................................... 360
Ping-Pong Buffering.......................................... 364
Register Summary ............................................ 365
Status and Configuration .................................. 360
Class Specifications and Drivers .............................. 378
Descriptors................................................................ 378
Endpoint Control ....................................................... 358
Enumeration.............................................................. 378
External Pull-up Resistors......................................... 356
Eye Pattern Test Enable ........................................... 356
Firmware and Drivers................................................ 375
Frame Number Registers.......................................... 359
Frames...................................................................... 377
Internal Pull-up Resistors.......................................... 356
Internal Transceiver .................................................. 354
Interrupts................................................................... 366
and USB Transactions...................................... 366
Layered Framework .................................................. 377
Oscillator Requirements............................................ 375
Overview ........................................................... 351, 377
Ping-Pong Buffer Configuration ................................ 356
Power........................................................................ 377
Power Modes ............................................................ 372
Bus Power Only ................................................ 372
Dual Power with Self-Power Dominance .......... 373
Self-Power Only................................................ 372
RAM .......................................................................... 359
Memory Map..................................................... 359
Speed........................................................................ 378
Status and Control .................................................... 352
Transfer Types.......................................................... 377
UFRMH:UFRML Registers ....................................... 359
USB. See Universal Serial Bus.
V
Voltage Reference (VR)
Specifications............................................................ 477
V
REF. SEE ADC Reference Voltage
VREFCON0 Register ........................................................ 346
VREFCON1 (Digital-to-Analog Converter Control 0)
Register..................................................................... 349
VREFCON2 (Digital-to-Analog Converter Control 1)
Register..................................................................... 350
W
Wake-up on Break............................................................ 287
Watchdog Timer (WDT)............................................ 385, 398
Associated Registers................................................ 399
Control Register........................................................ 399
Programming Considerations ................................... 398
WCOL ....................................................... 245, 248, 250, 252
WCOL Status Flag.................................... 245, 248, 250, 252
WDTCON Register ........................................................... 399
WWW Address ................................................................. 531
WWW, On-Line Support ....................................................... 9
X
XORLW ............................................................................ 445
XORWF ............................................................................ 446