Datasheet

PIC18(L)F2X/45K50
DS30684A-page 528  2012 Microchip Technology Inc.
Reads and Writes in 16-Bit Mode ............................. 162
Source Edge Select (T0SE Bit)................................. 162
Source Select (T0CS Bit)..........................................162
Switching Prescaler Assignment............................... 163
Timer1...............................................................................165
Associated registers..................................................176
Asynchronous Counter Mode ................................... 167
Reading and Writing ......................................... 167
Clock Source Selection............................................. 166
Interrupt..................................................................... 170
Operation .................................................................. 166
Operation During Sleep ............................................ 170
Oscillator ................................................................... 167
Prescaler................................................................... 167
Timer1 Gate
Selecting Source...............................................168
TMR1H Register .......................................................165
TMR1L Register........................................................ 165
Timer2
Associated registers..................................................180
Timer2/4/6......................................................................... 177
Associated registers..................................................180
Timers
Timer1
T1CON..............................................................174
T1GCON...........................................................175
Timing Diagrams
A/D Conversion.........................................................496
Acknowledge Sequence ........................................... 252
Asynchronous Reception .......................................... 277
Asynchronous Transmission ..................................... 272
Asynchronous Transmission (Back to Back) ............ 273
Auto Wake-up Bit (WUE) During Normal Operation . 288
Auto Wake-up Bit (WUE) During Sleep .................... 288
Automatic Baud Rate Calculator............................... 287
Baud Rate Generator with Clock Arbitration ............. 245
BRG Reset Due to SDA Arbitration During Start
Condition........................................................... 256
Brown-out Reset (BOR) ............................................ 484
Bus Collision During a Repeated Start Condition
(Case 1) ............................................................257
Bus Collision During a Repeated Start Condition
(Case 2) ............................................................257
Bus Collision During a Start Condition (SCL = 0) .....256
Bus Collision During a Stop Condition (Case 1) .......258
Bus Collision During a Stop Condition (Case 2) .......258
Bus Collision During Start Condition (SDA only) ...... 255
Bus Collision for Transmit and Acknowledge............ 254
Capture/Compare/PWM (CCP).................................486
CLKO and I/O ........................................................... 483
Clock Synchronization .............................................. 242
Clock/Instruction Cycle ............................................... 82
Comparator Output ................................................... 313
EUSART Synchronous Receive (Master/Slave) ....... 495
EUSART Synchronous Transmission
(Master/Slave)...................................................495
Example SPI Master Mode (CKE = 0) ...................... 487
Example SPI Master Mode (CKE = 1) ...................... 488
Example SPI Master Mode Timing ........................... 487
Example SPI Slave Mode (CKE = 0) ........................ 489
Example SPI Slave Mode (CKE = 1) ........................ 490
External Clock (All Modes except PLL)..................... 481
Fail-Safe Clock Monitor (FSCM) ................................. 48
First Start Bit Timing ................................................. 246
Full-Bridge PWM Output ........................................... 197
Half-Bridge PWM Output .................................. 195, 201
High/Low-Voltage Detect Characteristics ................. 477
High-Voltage Detect Operation (VDIRMAG = 1) ...... 382
I
2
C Bus Data............................................................. 491
I
2
C Bus Start/Stop Bits ............................................. 490
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 249
I
2
C Master Mode (7-Bit Reception)........................... 251
I
2
C Stop Condition Receive or Transmit Mode......... 252
Internal Oscillator Switch Timing ................................ 46
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 381
Master SSP I
2
C Bus Data......................................... 493
Master SSP I
2
C Bus Start/Stop Bits ......................... 493
PWM Auto-shutdown................................................ 200
Firmware Restart .............................................. 200
PWM Direction Change ............................................ 198
PWM Direction Change at Near 100% Duty Cycle... 199
PWM Output (Active-High) ....................................... 193
PWM Output (Active-Low) ........................................ 194
Repeat Start Condition ............................................. 247
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST), Power-up Timer (PWRT) ............ 484
Send Break Character Sequence............................. 289
Slow Rise Time (MCLR
Tied to VDD, VDD Rise >
T
PWRT)................................................................ 73
SPI Mode (Master Mode).......................................... 219
Synchronous Reception (Master Mode, SREN) ....... 294
Synchronous Transmission ...................................... 291
Synchronous Transmission (Through TXEN) ........... 291
Time-out Sequence on POR w/PLL Enabled
(MCLR
Tied to VDD) ........................................... 74
Time-out Sequence on Power-up (MCLR
Not
Tied to V
DD, Case 1) .......................................... 72
Time-out Sequence on Power-up (MCLR
Not
Tied to V
DD, Case 2) .......................................... 73
Time-out Sequence on Power-up (MCLR
Tied
to V
DD, VDD Rise < TPWRT) ................................ 72
Timer0 and Timer1 External Clock ........................... 485
Timer1 Incrementing Edge ....................................... 171
Transition for Entry to SEC_RUN Mode ..................... 57
Transition for Entry to Sleep Mode ............................. 60
Transition for Wake from Sleep (HSPLL) ................... 60
Transition from RC_RUN Mode to PRI_RUN Mode... 58
Transition from SEC_RUN Mode to PRI_RUN
Mode (HSPLL).................................................... 57
Transition Timing for Entry to Idle Mode..................... 61
Transition Timing for Wake from Idle to Run Mode .... 61
Timing Diagrams and Specifications ................................ 481
A/D Conversion Requirements ................................. 497
Capture/Compare/PWM Requirements .................... 487
CLKO and I/O Requirements.................................... 483
EUSART Synchronous Receive Requirements........ 495
EUSART Synchronous Transmission Requirements 495
Example SPI Mode Requirements
(Master Mode, CKE = 0)................................... 488
(Slave Mode, CKE = 0)..................................... 489
External Clock Requirements ................................... 481
I
2
C Bus Data Requirements (Slave Mode) ............... 492
I
2
C Bus Start/Stop Bits Requirements (Slave Mode) 491
Master SSP I
2
C Bus Data Requirements ................. 494
Master SSP I
2
C Bus Start/Stop Bits Requirements.. 493
PLL Clock ................................................................. 482
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements ................................................... 485
Timer0 and Timer1 External Clock Requirements.... 486