Datasheet

PIC18(L)F2X/45K50
DS30684A-page 524  2012 Microchip Technology Inc.
Synchronous Slave Mode
Associated Registers, Receive ......................... 297
Reception..........................................................297
Transmission..................................................... 295
Extended Instruction Set
ADDFSR ...................................................................448
ADDULNK................................................................. 448
and Using MPLAB Tools........................................... 454
CALLW......................................................................449
Considerations for Use .............................................452
MOVSF ..................................................................... 449
MOVSS ..................................................................... 450
PUSHL ......................................................................450
SUBFSR ...................................................................451
SUBULNK ................................................................. 451
Syntax .......................................................................447
F
Fail-Safe Clock Monitor............................................... 47, 385
Fail-Safe Condition Clearing ....................................... 47
Fail-Safe Detection .....................................................47
Fail-Safe Operation.....................................................47
Reset or Wake-up from Sleep..................................... 47
Fast Register Stack.............................................................80
Fixed Voltage Reference (FVR)
Associated Registers ................................................ 346
Flash Program Memory....................................................... 99
Associated Registers ................................................ 107
Control Registers ......................................................100
EECON1 and EECON2 .................................... 100
TABLAT (Table Latch) Register........................ 102
TBLPTR (Table Pointer) Register.....................102
Erase Sequence ....................................................... 104
Erasing...................................................................... 104
Operation During Code-Protect ................................ 107
Reading..................................................................... 103
Table Pointer
Boundaries Based on Operation....................... 102
Table Pointer Boundaries ......................................... 102
Table Reads and Table Writes ................................... 99
Write Sequence ........................................................ 105
Writing To.................................................................. 105
Protection Against Spurious Writes .................. 107
Unexpected Termination................................... 107
Write Verify ....................................................... 107
G
GOTO................................................................................ 426
Guidelines for Getting Started with PIC18(L)F2X/45K50
Microcontrollers.......................................................... 25
H
Hardware Multiplier ...........................................................115
Introduction ............................................................... 115
Operation .................................................................. 115
Performance Comparison .........................................115
High/Low-Voltage Detect ..................................................379
Applications...............................................................382
Associated Registers ................................................ 383
Characteristics .......................................................... 478
Current Consumption................................................ 381
Effects of a Reset...................................................... 383
Operation .................................................................. 380
During Sleep .....................................................383
Setup......................................................................... 381
Start-up Time ............................................................ 381
Typical Low-Voltage Detect Application ................... 382
HLVD. See High/Low-Voltage Detect............................... 379
I
I
2
C Mode (MSSP)
Bus Collision
During a Repeated Start Condition................... 257
During a Stop Condition ................................... 258
Effects of a Reset ..................................................... 253
I
2
C Clock Rate w/BRG.............................................. 260
Multi-Master Communication, Bus Collision and
Arbitration ......................................................... 254
Multi-Master Mode.................................................... 253
Stop Condition Timing .............................................. 252
I
2
C Mode (MSSPx)
Acknowledge Sequence Timing ............................... 252
Master Mode
Operation.......................................................... 244
Reception ......................................................... 250
Start Condition Timing .............................. 246, 247
Transmission .................................................... 248
Read/Write Bit Information (R/W
Bit) ........................ 229
Slave Mode
Transmission .................................................... 234
Sleep Operation........................................................ 253
ID Locations.............................................................. 385, 403
INCF ................................................................................. 426
INCFSZ............................................................................. 427
In-Circuit Debugger........................................................... 403
In-Circuit Serial Programming (ICSP)....................... 385, 403
Indexed Literal Offset Addressing
and Standard PIC18 Instructions.............................. 452
Indexed Literal Offset Mode.............................................. 452
Indirect Addressing ............................................................. 95
INFSNZ............................................................................. 427
Instruction Cycle ................................................................. 82
Clocking Scheme........................................................ 82
Instruction Flow/Pipelining .................................................. 82
Instruction Set................................................................... 405
ADDLW..................................................................... 411
ADDWF..................................................................... 411
ADDWF (Indexed Literal Offset Mode) ..................... 453
ADDWFC .................................................................. 412
ANDLW..................................................................... 412
ANDWF..................................................................... 413
BC............................................................................. 413
BCF .......................................................................... 414
BN............................................................................. 414
BNC .......................................................................... 415
BNN .......................................................................... 415
BNOV ....................................................................... 416
BNZ .......................................................................... 416
BOV .......................................................................... 419
BRA .......................................................................... 417
BSF........................................................................... 417
BSF (Indexed Literal Offset Mode) ........................... 453
BTFSC...................................................................... 418
BTFSS ...................................................................... 418
BTG .......................................................................... 419
BZ ............................................................................. 420
CALL......................................................................... 420
CLRF ........................................................................ 421
CLRWDT .................................................................. 421
COMF ....................................................................... 422
CPFSEQ................................................................... 422
CPFSGT ................................................................... 423