Datasheet
2012 Microchip Technology Inc. DS30684A-page 497
PIC18(L)F2X/45K50
TABLE 29-23: A/D CONVERSION REQUIREMENTS (PIC18(L)F2X/45K50)
Standard Operating Conditions (unless otherwise stated)
Operating temperature Tested at +25°C
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
130 T
AD A/D Clock Period 1 — 25 s-40C to +85C
131 TCNV
Conversion Time
(not including acquisition time) (Note 1)
12 — 12 TAD
132 TACQ
Acquisition Time (Note 2) 1.4 — — sVDD = 3V, Rs = 50
135 T
SWC
Switching Time from Convert Sample — — (Note 3)
136 T
DIS
Discharge Time 2 — 2 TAD
Note 1: ADRES register may be read on the following TCY cycle.
2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50 .
3: On the following cycle of the device clock.