Datasheet

 2012 Microchip Technology Inc. DS30684A-page 495
PIC18(L)F2X/45K50
FIGURE 29-19: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
FIGURE 29-20: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
121
121
120
122
TX/CK
RX/DT
pin
pin
Note: Refer to Figure 29-4 for load conditions.
TABLE 29-20: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param.
No.
Symbol Characteristic Min Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
—40ns
121 Tckrf Clock Out Rise Time and Fall Time
(Master mode)
—20ns
122 Tdtrf Data Out Rise Time and Fall Time
—20ns
125
126
TX/CK
RX/DT
pin
pin
Note: Refer to Figure 29-4 for load conditions.
TABLE 29-21: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 TdtV2ckl
SYNC RCV (MASTER & SLAVE)
Data Setup before CK  (DT setup time) 10 — ns
126 TckL2dtl
Data Hold after CK  (DT hold time) 15 — ns