Datasheet

PIC18(L)F2X/45K50
DS30684A-page 42  2012 Microchip Technology Inc.
3.8 PLL Frequency Multiplier
A Phase-Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from the crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator.
3.8.1 PLL IN EXTERNAL OSCILLATOR
MODES
The PLL can be enabled for any of the external
oscillator modes using the OSC1/OSC2 pins. Medium-
power and low-power oscillator mode selections in
CONFIG1H<3:0> (FOSC) should not be used with the
PLL. The PLL can be enabled using the CFGPLLEN/
PLLSEL configuration bits in the CONFIG1L register,
or by software using the PLLEN/SPLLMULT special
function register bits in OSCCON2 and OSCTUNE,
respectively.
A selectable 3x or 4x frequency multiplier circuit is
provided. This gives greater flexibility in source clock
frequencies that can be used. Source clock
frequencies between 8 and 12 MHz may use the 4x
frequency multiplier to achieve operating speeds of 32
through 48 MHz. A source clock frequency of 16 MHz
may use the 3x frequency multiplier to achieve 48
MHz operating speed.
3.8.2 PLL IN HFINTOSC MODES
The PLL can be enabled using the HFINTOSC internal
oscillator block. The frequency select bits (IRCF<2:0>
in the OSCCON register) should be configured for 16
MHz when using the HFINTOSC with 3x frequency
multiplier. The IRCF bits should be configured for 8
MHz when using HFINTOSC with 4x frequency
multiplier.
3.9 Effects of Power-Managed Modes
on the Various Clock Sources
For more information about the modes discussed in this
section see Section 4.0 “Power-Managed Modes”. A
quick reference list is also available in Tab le 4 - 1 .
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the secondary oscillator (SOSC) is
operating and providing the device clock. The
secondary oscillator may also run in all power-
managed modes if required to clock Timer1 or Timer3.
In internal oscillator modes (INTOSC_RUN and
INTOSC_IDLE), the internal oscillator block provides
the device clock source. The 31.25 kHz INTRC output
can be used directly to provide the clock and may be
enabled to support various special features, regardless
of the power-managed mode (see Section 26.3
“Watchdog Timer (WDT)”, Section 3.12 “Two-
Speed Clock Start-up Mode” and Section 3.13 “Fail-
Safe Clock Monitor” for more information on WDT,
Fail-Safe Clock Monitor and Two-Speed Start-up). The
HFINTOSC output may be used directly to clock the
device or may be divided down by the postscaler. The
HFINTOSC output is disabled when the clock is
provided directly from the INTRC output.
When the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation.
Other features may be operating that do not require a
device clock source (i.e., SSP slave, INTn pins and
others). Peripherals that may add significant current
consumption are listed in Section 29.8 “DC
Characteristics: Input/Output Characteristics,
PIC18(L)F2X/45K50”.