Datasheet

PIC18(L)F2X/45K50
DS30684A-page 400  2012 Microchip Technology Inc.
26.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
®
microcontroller devices.
The user program memory is divided into three or five
blocks, depending on the device. One of these is a
Boot Block of 0.5K or 2K bytes, depending on the
device. The remainder of the memory is divided into
individual blocks on binary boundaries.
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 26-2 shows the program memory organization
for 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 26-5.
FIGURE 26-2: CODE-PROTECTED PROGRAM MEMORY FOR PIC18(L)F2X/45K50
MEMORY SIZE/DEVICE
Block Code Protection
Controlled By:
16 Kbytes
(PIC18(L)F24K50)
32 Kbytes
(PIC18(L)FX5K50)
Boot Block
(000h-7FFh)
Boot Block
(000h-7FFh)
CPB, WRTB, EBTRB
Block 0
(800h-1FFFh)
Block 0
(800h-1FFFh)
CP0, WRT0, EBTR0
Block 1
(2000h-3FFFh)
Block 1
(2000h-3FFFh)
CP1, WRT1, EBTR1
Unimplemented
Read ‘0’s
(4000h-1FFFFFh)
Block 2
(4000h-5FFFh)
CP2, WRT2, EBTR2
Block 3
(6000h-7FFFh)
CP3, WRT3, EBTR3
Unimplemented
Read ‘0’s
(8000h-1FFFFFh)
(Unimplemented
Memory Space)
TABLE 26-5: CONFIGURATION REGISTERS ASSOCIATED WITH CODE PROTECTION
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L — — — —CP3
(1)
CP2
(1)
CP1 CP0
300009h CONFIG5H CPD CPB — — — — — —
30000Ah CONFIG6L
— — — —WRT3
(1)
WRT2
(1)
WRT1 WRT0
30000Bh CONFIG6H WRTD WRTB WRTC
(2)
— — — — —
30000Ch CONFIG7L
— — — — EBTR3
(1)
EBTR2
(1)
EBTR1 EBTR0
30000Dh CONFIG7H
— EBTRB — — — — — —
Legend: Shaded bits are unimplemented.
Note 1: Available on PIC18(L)F45K50 and PIC18(L)F25K50 devices only.
2: In User mode, this bit is read-only and cannot be self-programmed.