Datasheet

PIC18(L)F2X/45K50
DS30684A-page 392  2012 Microchip Technology Inc.
REGISTER 26-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW
R/P-1 R/P-0 R/P-1 U-0 U-0 R/P-1 U-0 R/P-1
DEBUG
(2)
XINST ICPRT
(3)
— —LVP
(1)
—STVREN
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7 DEBUG
: Background Debugger Enable bit
(2)
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6 XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
bit 5 ICPRT: Dedicated In-Circuit (ICD) Port Enable bit
(3)
1 = ICPORT enabled (ICD function on dedicated ICD pins)
0 = ICPORT disabled (ICD function on default ICD pins, RB6/7)
bit 4-3 Unimplemented: Read as ‘0’
bit 2 LVP: Single-Supply ICSP Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
bit 1 Unimplemented: Read as ‘0’
bit 0 STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Note 1: Can only be changed by a programmer in high-voltage programming mode.
2: The DEBUG
bit is managed automatically by device development tools including debuggers and programmers. For
normal device operations, this bit should be maintained as a ‘1’.
3: Available only on 44-pin TQFP package devices. Program this bit clear on all other devices.