Datasheet

 2012 Microchip Technology Inc. DS30684A-page 387
PIC18(L)F2X/45K50
26.2 Register Definitions: Configuration Word
REGISTER 26-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW
U-0 U-0 R/P-0 R/P-0 R/P-0 U-0 R/P-0 R/P-0
— —
LS48MHZ CPUDIV<1:0>
—
CFGPLLEN PLLSEL
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 LS48MHZ: USB Low-Speed Clock Selection bit
Selects the clock source for Low-speed USB operation
1 = System clock is expected at 48 MHz, FS/LS USB clock divide-by is set to 8
0 = System clock is expected at 24 MHz, FS/LS USB clock divide-by is set to 4
bit 4-3 CPUDIV<1:0>: CPU System Clock Selection bits
11 = CPU system clock divided by 6
10 = CPU system clock divided by 3
01 = CPU system clock divided by 2
00 = No CPU system clock divide
bit 2 Unimplemented: Read as ‘0’
bit 1 CFGPLLEN: PLL Enable bit
(1)
1 = Oscillator multiplied by 3 or 4, depending on the PLLSEL bit
0 = Oscillator used directly
bit 0 PLLSEL: PLL Multiplier Selection bit
1 = Output frequency is 3x the input frequency
0 = Output frequency is 4x the input frequency
Note 1: See Table 3-1 for conditions under which the CFGPLLEN fuse is available.