Datasheet

PIC18(L)F2X/45K50

DS30684A-page 36  2012 Microchip Technology Inc.

R-0/0 R-0/q R/W-0 R/W-0/0 R/W-0/u R/W-1/1 R-0/0 R-0/0

PLLRDY SOSCRUN

INTSRC

PLLEN SOSCGO

(1)

PRISD HFIOFR LFIOFS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

bit 7 PLLRDY: PLL Run Status bit

1 = System clock comes from PLL

0 = System clock comes from an oscillator, other than PLL

bit 6 SOSCRUN: SOSC Run Status bit

1 = System clock comes from secondary SOSC

0 = System clock comes from an oscillator, other than SOSC

bit 5 INTSRC: HFINTOSC Divided by 512 Enable bit

1 = HFINTOSC used as the 31.25 kHz system clock reference – high accuracy

0 = INTRC used as the 31.25 kHz system clock reference – low power.

bit 4 PLLEN: Software PLL Enable bit

If FOSC<3:0> = 100x, 010x or 001x

1 = PLL enabled

0 = PLL disabled

Else,

No effect on PLL operation.

bit 3 SOSCGO

(1)

: Secondary Oscillator Start Control bit

1 = Secondary oscillator is enabled.

0 = Secondary oscillator is shut off if no other sources are requesting it.

bit 2 PRISD: Primary Oscillator Drive Circuit Shutdown bit

1 = Oscillator drive circuit on

0 = Oscillator drive circuit off (zero power)

bit 1 HFIOFR: HFINTOSC Status bit

1 = HFINTOSC is running

0 = HFINTOSC is not running

bit 0 LFIOFS: INTRC Frequency Stable bit

1 = INTRC is stable

0 = INTRC is not stable

Note 1: The SOSCGO bit is only reset on a POR Reset.