Datasheet

PIC18(L)F2X/45K50
DS30684A-page 34  2012 Microchip Technology Inc.
FIGURE 3-2: INTERNAL OSCILLATOR
MUX BLOCK DIAGRAM
FIGURE 3-3: SECONDARY OSCILLATOR AND EXTERNAL CLOCK INPUTS
111
110
101
100
000
INTOSC
31.25 kHz
1
0
IRCF<2:0>
INTSRC
HF-16 MHz
HF-8 MHz
HF-4 MHz
HF-2 MHz
HF-1 MHz
LF-31.25 kHz
HF-31.25 kHz
3
011
HF-500 kHz
010
HF-250 kHz
001
TABLE 3-1: PLL_SELECT TRUTH TABLE
Primary Clock MUX Source FOSC<3:0> CFGPLLEN PLLSEL PLLEN SPLLMULT PLL_Select
External Clock (ECHIO/ECHCLKO)
010x 1
1x x3xPLL
(1)
0x x4xPLL
(2)
HS Crystal (HSH) 0010 0 x
1
1 3xPLL
(1)
0 4xPLL
(2)
INTOSC (INTOSCIO, INTOSCCLKO) 100x 0 x OFF
F
OSC (all other modes) xxxx x x x x OFF
Note 1: The input clock source must be 16 MHz when 3xPLL is used.
2: The input clock source must be 8 MHz to 12 MHz when 4xPLL is used.
0
1
1
0
EN
SOSCEN
SOSCGO
T1CON<3>
T3CON<3>
To Clock Switch Module
SOSCOUT
Secondary
Oscillator
SOSCI
SOSCO
T1CKI
T3G
T3CKI
SOSCEN
SOSCEN
SOSCEN
T3G
T3CMX
T1G
T3CKI
T1G
1
0
T1CON<3>
T1CLK_EXT_SRC
T3CLK_EXT_SRC
T3CON<3>