Datasheet

 2012 Microchip Technology Inc. DS30684A-page 33
PIC18(L)F2X/45K50
3.2 Oscillator Control
The OSCCON, OSCCON2 and OSCTUNE registers
(Register 3-1 to Register 3-3) control several aspects
of the device clock’s operation, both in full-power
operation and in power-managed modes.
• Main System Clock Selection (SCS)
• Primary Oscillator Circuit Shutdown (PRISD)
• Secondary Oscillator Enable (SOSCGO)
• Primary Clock Frequency multiplier (PLLEN)
• Internal Frequency selection bits (IRCF, INTSRC)
• Clock Status bits (OSTS, HFIOFS, LFIOFS,
SOSCRUN, PLLRDY)
• Power management selection (IDLEN)
3.2.1 MAIN SYSTEM CLOCK SELECTION
The System Clock Select bits, SCS<1:0>, select the
main clock source. The available clock sources are:
• Primary clock defined by the FOSC<3:0> bits of
CONFIG1H. The primary clock can be the primary
oscillator, an external clock, or the internal
oscillator block.
• Secondary clock (secondary oscillator)
• Internal oscillator block (HFINTOSC and INTRC).
The clock source changes immediately after one or
more of the bits is written to, following a brief clock
transition interval. The SCS bits are cleared to select
the primary clock on all forms of Reset.
3.2.2 INTERNAL FREQUENCY
SELECTION
The Internal Oscillator Frequency Select bits
(IRCF<2:0>) select the frequency output of the internal
oscillator block. The choices are the INTRC source
(31.25 kHz) and the HFINTOSC source (16 MHz) or
one of the frequencies derived from the HFINTOSC
postscaler (31.25 kHz to 16 MHz). If the internal oscil-
lator block is supplying the main clock, changing the
states of these bits will have an immediate change on
the internal oscillator’s output. On device Resets, the
output frequency of the internal oscillator is set to the
default frequency of 1 MHz.
3.2.3 LOW-FREQUENCY SELECTION
When a nominal output frequency of 31.25 kHz is
selected (IRCF<2:0> = 000), users may choose
which internal oscillator acts as the source. This is
done with the INTSRC bit of the OSCCON2<5>
register. See Figure 3-2 and Register 3-1 for specific
31.25 kHz selection. This option allows users to
select a 31.25 kHz clock (based on HFINTOSC) that
can be tuned using the TUN<6:0> bits in the
OSCTUNE register, while maintaining power savings
with a very low clock speed. INTRC always remains
the clock source for features such as the Watchdog
Timer and the Fail-Safe Clock Monitor, regardless of
the setting of the INTSRC bit.
This option allows users to select the tunable and more
precise HFINTOSC as a clock source, while
maintaining power savings with a very low clock speed.
3.2.4 POWER MANAGEMENT
The IDLEN bit of the OSCCON register determines
whether the device goes into Sleep mode or one of the
Idle modes when the SLEEP instruction is executed.