Datasheet
2012 Microchip Technology Inc. DS30684A-page 297
PIC18(L)F2X/45K50
17.5.2.3 EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 17.5.1.6 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
never Idle
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREGx register. If the RCIE enable bit is set,
the interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE/GIEH bit is
also set, the program will branch to the interrupt vector.
17.5.2.4 Synchronous Slave Reception
Setup:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Set the RX/DT and TX/CK TRIS controls to ‘1’.
3. If using interrupts, ensure that the GIE/GIEH
and PEIE/GIEL bits of the INTCON register are
set and set the RCIE bit.
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the CREN bit to enable reception.
6. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTAx
register.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCREGx register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTAx
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 17-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
BAUDCON1
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 281
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120
IPR1
ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129
PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 126
PIR1
ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 123
PMD0 —UARTMDUSBMD ACTMD — TMR3MD TMR2MD TMR1MD 64
RCREG1 EUSART Receive Register
—
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 280
SPBRG1 EUSART Baud Rate Generator, Low Byte
—
SPBRGH1 EUSART Baud Rate Generator, High Byte
—
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 279
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception.