Datasheet

PIC18(L)F2X/45K50
DS30684A-page 294  2012 Microchip Technology Inc.
FIGURE 17-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RCREGx
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)
TABLE 17-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
BAUDCON1
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 281
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120
IPR1
ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129
PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 126
PIR1
ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 123
PMD0 —UARTMDUSBMD ACTMD — TMR3MD TMR2MD TMR1MD 64
RCREG1 EUSART Receive Register
—
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 280
SPBRG1 EUSART Baud Rate Generator, Low Byte
—
SPBRGH1 EUSART Baud Rate Generator, High Byte
—
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 279
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.