Datasheet

PIC18(L)F2X/45K50
DS30684A-page 274  2012 Microchip Technology Inc.
17.1.2 EUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode would typically be used in
RS-232 systems. The receiver block diagram is shown
in Figure 17-2. The data is received on the RX/DT pin
and drives the data recovery block. The data recovery
block is actually a high-speed shifter operating at 16
times the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all eight
or nine bits of the character have been shifted in, they
are immediately transferred to a two character First-In-
First-Out (FIFO) memory. The FIFO buffering allows
reception of two complete characters and the start of a
third character before software must start servicing the
EUSART receiver. The FIFO and RSR registers are not
directly accessible by software. Access to the received
data is via the RCREGx register.
17.1.2.1 Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTAx register enables
the receiver circuitry of the EUSART. Clearing the
SYNC bit of the TXSTAx register configures the
EUSART for asynchronous operation. Setting the
SPEN bit of the RCSTAx register enables the
EUSART. The RX/DT I/O pin must be configured as an
input by setting the corresponding TRIS control bit. If
the RX/DT pin is shared with an analog peripheral the
analog I/O function must be disabled by clearing the
corresponding ANSEL bit.
17.1.2.2 Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. See Section 17.1.2.5 “Receive Framing
Error” for more information on framing errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREGx register.
17.1.2.3 Receive Data Polarity
The polarity of the receive data can be controlled with
the RXDTP bit of the BAUDCONx register. The default
state of this bit is ‘0’ which selects high true receive Idle
and data bits. Setting the RXDTP bit to ‘1’ will invert the
receive data resulting in low true Idle and data bits. The
RXDTP bit controls receive data polarity only in
Asynchronous mode. In Synchronous mode the
RXDTP bit has a different function.
Note: If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 17.1.2.6
“Receive Overrun Error” for more
information on overrun errors.