Datasheet

 2012 Microchip Technology Inc. DS30684A-page 273
PIC18(L)F2X/45K50
FIGURE 17-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Transmit Shift Reg
Write to TXREGx
BRG Output
(Shift Clock)
TX/CK
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Start bit
Stop bit
Start bit
Transmit Shift Reg
Word 1
Word 2
bit 0 bit 1
bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
pin
TABLE 17-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
BAUDCON1
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 281
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120
IPR1
ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129
PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 126
PIR1
ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 123
PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 64
RCSTA1
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 280
SPBRG1 EUSART Baud Rate Generator, Low Byte
—
SPBRGH1 EUSART Baud Rate Generator, High Byte
—
TXREG1 EUSART Transmit Register
—
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 279
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission.