Datasheet

 2012 Microchip Technology Inc. DS30684A-page 263
PIC18(L)F2X/45K50
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = F
OSC/4
0001 = SPI Master mode, clock = F
OSC/16
0010 = SPI Master mode, clock = F
OSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin, SS
pin control enabled
0101 = SPI Slave mode, clock = SCK pin, SS
pin control disabled, SS can be used as I/O pin
0110 = I
2
C Slave mode, 7-bit address
0111 = I
2
C Slave mode, 10-bit address
1000 = I
2
C Master mode, clock = FOSC / (4 * (SSPxADD+1))
(4)
1001 = Reserved
1010 = SPI Master mode, clock = F
OSC/(4 * (SSPxADD+1))
1011 = I
2
C firmware controlled Master mode (slave idle)
1100 = Reserved
1101 = Reserved
1110 = I
2
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I
2
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPxBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: When enabled, the SDA and SCL pins must be configured as inputs.
4: SSPxADD values of 0, 1 or 2 are not supported for I
2
C mode.
REGISTER 16-2: SSPxCON1: SSPx CONTROL REGISTER 1 (CONTINUED)