Datasheet

 2012 Microchip Technology Inc. DS30684A-page 223
PIC18(L)F2X/45K50
16.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmission/
reception will remain in that state until the device
wakes. After the device returns to Run mode, the
module will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the
MSSP interrupt flag bit will be set and if enabled, will
wake the device.
TABLE 16-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
ANSELA
— —
ANSA5
—
ANSA3 ANSA2 ANSA1 ANSA0 154
ANSELB
— —
ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 155
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120
IPR1
ACTIP
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129
PIE1
ACTIE
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 126
PIR1
ACTIF
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 123
PMD1
—
MSSPMD
CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 65
SSP1BUF SSP1 Receive Buffer/Transmit Register
—
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 262
SSP1CON3
ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 265
SSP1STAT SMP CKE D/A P S R/W UA BF 261
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 156
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156
TRISC
TRISC7 TRISC6
— — —
TRISC2 TRISC1 TRISC0 156
Legend: Shaded bits are not used by the MSSP in SPI mode.