Datasheet

PIC18(L)F2X/45K50
DS30684A-page 214  2012 Microchip Technology Inc.
The I
2
C interface supports the following modes and
features:
•Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
•Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 16-2 is a block diagram of the I
2
C interface
module in Master mode. Figure 16-3 is a diagram of the
I
2
C interface module in Slave mode.
FIGURE 16-2: MSSP BLOCK DIAGRAM (I
2
C™ MASTER MODE)
Read Write
SSPxSR
Start bit, Stop bit,
Start bit Detect,
SSPxBUF
Internal
Data Bus
Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV
Shift
Clock
MSb
LSb
SDA
Acknowledge
Generate (SSPxCON2)
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL
SCL in
Bus Collision
SDA in
Receive Enable (RCEN)
Clock Cntl
Clock Arbitrate/BCOL Detect
(Hold off clock source)
[SSPxM 3:0]
Baud Rate
Reset SEN, PEN (SSPxCON2)
Generator
(SSPxADD)
Address Match Detect
Set SSPIF, BCLIF