Datasheet

 2012 Microchip Technology Inc. DS30684A-page 189
PIC18(L)F2X/45K50
5. Configure and start the 8-bit Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIR1 register. See Note 1 below.
• Configure the T2CKPS bits of the T2CON
register with the Timer prescale value.
• Enable the Timer by setting the TMR2ON
bit of the T2CON register.
6. Enable PWM output pin:
• Wait until the Timer overflows and the
TMR2IF bit of the PIR1 register is set. See
Note 1 below.
• Enable the CCPx pin output driver by
clearing the associated TRIS bit.
15.3.3 PWM PERIOD
The PWM period is specified by the PR2 register of 8-bit
Timer2. The PWM period can be calculated using the
formula of Equation 15-1.
EQUATION 15-1: PWM PERIOD
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH.
15.3.4 PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPRxL register and
DCxB<1:0> bits of the CCPxCON register. The
CCPRxL contains the eight MSbs and the DCxB<1:0>
bits of the CCPxCON register contain the two LSbs.
CCPRxL and DCxB<1:0> bits of the CCPxCON
register can be written to at any time. The duty cycle
value is not latched into CCPRxH until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPRxH
register is read-only.
Equation 15-2 is used to calculate the PWM pulse
width.
Equation 15-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 15-2: PULSE WIDTH
EQUATION 15-3: DUTY CYCLE RATIO
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (F
OSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 15-4).
Note 1: In order to send a complete duty cycle
and period on the first PWM output, the
above steps must be included in the
setup sequence. If it is not critical to start
with a complete PWM signal on the first
output, then step 5 may be ignored.
Note: The Timer postscaler (see Section 14.0
“Timer2 Module”) is not used in the
determination of the PWM frequency.
PWM Period PR21+4TOSC =
(TMR2 Prescale Value)
Note 1: TOSC = 1/FOSC
Pulse Width CCPRxL:CCPxCON<5:4>  =
T
OSC  (TMR2 Prescale Value)
Duty Cycle Ratio
CCPRxL:CCPxCON<5:4>
4PR2 1+
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