Datasheet

 2012 Microchip Technology Inc. DS30684A-page 185
PIC18(L)F2X/45K50
15.2 Compare Mode
The Compare mode function described in this section
is identical for all CCP and ECCP modules available on
this device family.
Compare mode makes use of the 16-bit Timer
resources, Timer1 and Timer3. The 16-bit value of the
CCPRxH:CCPRxL register pair is constantly compared
against the 16-bit value of the TMRxH:TMRxL register
pair. When a match occurs, one of the following events
can occur:
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
All Compare modes can generate an interrupt.
Figure 15-2 shows a simplified diagram of the
Compare operation.
FIGURE 15-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
15.2.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
Some CCPx outputs are multiplexed on a couple of
pins. Table 15-1 shows the CCP output pin
multiplexing. Selection of the output pin is determined
by the CCPxMX bits in Configuration register 3H
(CONFIG3H). Refer to Register 26-5 for more details.
15.2.2 TimerX MODE RESOURCE
In Compare mode, 16-bit TimerX resource must be
running in either Timer mode or Synchronized Counter
mode. The compare operation may not work in
Asynchronous Counter mode.
See Section 13.0 “Timer1/3 Module with Gate
Control” for more information on configuring the 16-bit
TimerX resources.
15.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCPxCON
register).
CCPRxH CCPRxL
TMRxH TMRxL
Comparator
QS
R
Output
Logic
Special Event Trigger
Set CCPxIF Interrupt Flag
(PIR
x)
Match
TRIS
CCPxM<3:0>
Mode Select
Output Enable
Pin
Special Event Trigger function on
• ECCP1 and CCP2 will:
- Reset TimerX – TMRxH:TMRxL = 0x0000
- TimerX Interrupt Flag, (TMRxIF) is not set
Additional Function on
• CCP2 will
- Set ADCON0<1>, GO/DONE
bit to start an ADC
Conversion if ADCON<0>, ADON = 1, and if
ADCON1<7>, TRIGSEL = 0.
CCPx
4
Note: Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
Note: Clocking TimerX from the system clock
(F
OSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, TimerX must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.