Datasheet

 2012 Microchip Technology Inc. DS30684A-page 173
PIC18(L)F2X/45K50
FIGURE 13-7: TIMER1/3 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
13.12 Peripheral Module Disable
When a peripheral module is not used or inactive, the
module can be disabled by setting the Module Disable
bit in the PMD registers. This will reduce power con-
sumption to an absolute minimum. Setting the PMD
bits holds the module in Reset and disconnects the
module’s clock source. The Module Disable bits for
Timer1 (TMR1MD) and Timer3 (TMR3MD) are in the
PMD0 Register. See Section 4.0 “Power-Managed
Modes” for more information.
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
Timer1/3
NN + 1
N + 2
TxGSPM
TxGGO/
DONE
Set by software
Cleared by hardware on
falling edge of TxGVAL
Set by hardware on
falling edge of TxGVAL
Cleared by software
Cleared by
software
TMRxGIF
TxGTM
Counting enabled on
rising edge of TxG
N + 4
N + 3