Datasheet

PIC18(L)F2X/45K50
DS30684A-page 152 2012 Microchip Technology Inc.
TABLE 11-13: PORTE I/O SUMMARY
Pin Function
TRIS
Setting
ANSEL
Setting
Pin
Type
Buffer
Type
Description
RE0/AN5 RE0 00O DIG LATE<0> data output; not affected by analog input.
10I ST PORTE<0> data input; disabled when analog input
enabled.
AN5 11I AN Analog input 5.
RE1/AN6 RE1 00O DIG LATE<1> data output; not affected by analog input.
10I ST PORTE<1> data input; disabled when analog input
enabled.
AN6 11I AN Analog input 6.
RE2/AN7 RE2 00O DIG LATE<2> data output; not affected by analog input.
10I ST PORTE<2> data input; disabled when analog input
enabled.
AN7 11I AN Analog input 7.
RE3/V
PP/MCLR
RE3 I ST PORTE<3> data input; enabled when Configuration bit
MCLRE = 0.
V
PP P AN Programming voltage input; always available
MCLR
——
I ST Active-low Master Clear (device Reset) input; enabled
when configuration bit MCLRE = 1.
Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal;
CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I
2
C
TM
= Schmitt Trigger input
with I
2
C.
TABLE 11-14: REGISTERS ASSOCIATED WITH PORTE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
ANSELE
(1)
ANSE2 ANSE1 ANSE0 156
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 TMR0IP IOCIP 121
LATE
(1)
LATE2 LATE1 LATE0 157
PORTE
—RE3
RE2
(1)
RE1
(1)
RE0
(1)
154
SLRCON —SLRE
(1)
SLRD
(1)
SLRC SLRB SLRA 159
TRISE WPUE3 TRISE2
(1)
TRISE1
(1)
TRISE0
(1)
156
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTE.
Note 1: Available on PIC18(L)F45K50 devices only.
TABLE 11-15: CONFIGURATION REGISTERS ASSOCIATED WITH PORTE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
CONFIG3H
MCLRE
SDOMX
T3CMX PBADEN CCP2MX 391
CONFIG4L
DEBUG XINST LVP
(1)
STRVEN 392
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for interrupts.
Note 1: Can only be changed when in high-voltage programming mode.