Datasheet

 2012 Microchip Technology Inc. DS30684A-page 147
PIC18(L)F2X/45K50
TABLE 11-9: REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
ANSELC ANSC7 ANSC6
— — — ANSC2 — — 155
ECCP1AS
ECCP1ASE ECCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 210
CCP1CON P1M<1:0>
DC1B<1:0> CCP1M<3:0> 206
CCP2CON
— — DC2B<1:0> CCP2M<3:0> 206
CTMUCONH CTMUEN
— CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 335
LATC LATC7 LATC6
— — — LATC2 LATC1 LATC0 157
PORTC RC7 RC6
— — — RC2 RC1 RC0 153
RCSTA1 SPEN
RX9 SREN CREN ADDEN FERR OERR RX9D 280
SLRCON
— — — SLRE
(1)
SLRD
(1)
SLRC SLRB SLRA 159
SSP1CON1
WCOL SSPOV SSPEN CKP SSPM<3:0> 262
T1CON TMR1CS<1:0>
T1CKPS<1:0> SOSCEN T1SYNC RD16 TMR1ON 174
T3CON TMR3CS<1:0>
T3CKPS<1:0> SOSCEN T3SYNC RD16 TMR3ON 174
T3GCON TMR3GE
T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS 175
TRISC TRISC7 TRISC6
— — — TRISC2 TRISC1 TRISC0 156
TXSTA1 CSRC
TX9 TXEN SYNC SENDB BRGH TRMT TX9D 279
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC.
Note 1: Available on PIC18(L)F45K50 devices only.
TABLE 11-10: CONFIGURATION REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
CONFIG3H
MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 391
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC.