Datasheet

 2012 Microchip Technology Inc. DS30684A-page 143
PIC18(L)F2X/45K50
TABLE 11-6: REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
ANSELB
— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 155
ECCP1AS
ECCP1ASE ECCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 210
CCP1CON P1M<1:0>
DC1B<1:0> CCP1M<3:0> 206
CCP2CON
— — DC2B<1:0> CCP2M<3:0> 206
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP 121
INTCON3 INT2IP INT1IP
— INT2IE INT1IE — INT2IF INT1IF 122
IOCB IOCB7 IOCB6 IOCB5 IOCB4
— — — — 158
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 157
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 153
SLRCON
— — — SLRE
(1)
SLRD
(1)
SLRC SLRB SLRA 159
T1GCON TMR1GE
T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 175
T3CON TMR3CS<1:0>
T3CKPS<1:0> SOSCEN T3SYNC RD16 TMR3ON 174
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 157
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB.
Note 1: Available on PIC18(L)F45K50 devices only.
TABLE 11-7: CONFIGURATION REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
CONFIG3H
MCLRE SDOMX —T3CMX — — PBADEN CCP2MX 391
CONFIG4L DEBUG
XINST ICPRT — —LVP
(1)
— STRVEN 392
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB.
Note 1: Can only be changed when in high voltage programming mode.