Datasheet

 2012 Microchip Technology Inc. DS30684A-page 141
PIC18(L)F2X/45K50
A mismatch condition will continue to set the IOCIF flag
bit. Reading or writing PORTB will end the mismatch
condition and allow the IOCIF bit to be cleared. The latch
holding the last read value is not affected by a MCLR
nor
Brown-out Reset. After either one of these Resets, the
IOCIF flag will continue to be set if a mismatch is present.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
11.3.3 ALTERNATE FUNCTIONS
PORTB is multiplexed with several peripheral functions
(Table 11-5). The pins have TTL input buffers. Some of
these pin functions can be relocated to alternate pins
using the Control fuse bits in CONFIG3H. RB3 is the
default pin for SDO. Clearing the SDOMX bit moves the
SDO pin function to RC7.
Two other pin functions, T3CKI and CCP2, can be
relocated from their default pins to PORTB pins by
clearing the control fuses in CONFIG3H. Clearing
T3CMX and CCP2MX moves the pin functions to RB5
and RB3, respectively.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the IOCIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all
bits of that port, care must be taken when
using multiple pins in Interrupt-on-Change
mode. Changes on one pin may not be
seen while servicing changes on another
pin.
TABLE 11-5: PORTB I/O SUMMARY
Pin Function
TRIS
Setting
ANSEL
Setting
Pin
Type
Buffer
Type
Description
RB0/INT0/FLT0
/
SRI/SDA/SDI/AN12
RB0 0xO DIG LATB<0> data output; not affected by analog input.
10 I TTL PORTB<0> data input; disabled when analog input
enabled.
INT0 10 I ST External interrupt 0.
FLT0
10 I ST PWM Fault input for ECCP auto-shutdown.
SRI 10 I ST SR latch input.
SDA 10I/O I
2
CI
2
C
TM
Data I/O (MSSP).
SDI 10 I ST SPI Data in (MSSP).
AN12 11 I AN Analog input 12.
RB1/INT1/P1C/
SCK/SCL/C12IN3-/
AN10
RB1 0xO DIG LATB<1> data output; not affected by analog input.
10 I TTL PORTB<1> data input; disabled when analog input
enabled.
INT1 10 I ST External Interrupt 1.
P1C
(3)
00O DIG Enhanced CCP1 PWM output 3.
SCK 00O DIG MSSP SPI Clock output.
10 I ST MSSP SPI Clock input.
SCL 00O DIG MSSP I
2
C
TM
Clock output.
10 II
2
C MSSP I
2
C
TM
Clock input.
C12IN3- 11 I AN Comparators C1 and C2 inverting input.
AN10 11 I AN Analog input 10.
Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal;
CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I
2
C
TM
= Schmitt Trigger input
with I
2
C.
Note 1: Default pin assignment for SDO when Configuration bit SDOMX is set.
2: Alternate pin assignment for T3CKI and CCP2 when Configuration bits T3CMX and CCP2MX are clear.
3: Function is on PORTD/PORTE for PIC18(L)F45K50 devices.