Datasheet

PIC18(L)F2X/45K50
DS30684A-page 14  2012 Microchip Technology Inc.
FIGURE 1-1: PIC18(L)F2X/45K50 FAMILY BLOCK DIAGRAM
Instruction
Decode and
Control
Data Latch
Data Memory
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PCLATU
PCU
Note 1: RE3 is only available when MCLR functionality is disabled.
2: OSC1/CLKIN and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 6.0 “Memory Organization” for additional information.
EUSART
Comparators
MSSP
10-bit
ADC
Timer2
Timer1
CTMUTimer0
USB
HLVD
ECCP1
BOR
Data
EEPROM
W
Instruction Bus <16>
STKPTR
Bank
8
State machine
control signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1
(2)
OSC2
(2)
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
MCLR
(1)
Block
INTRC
Oscillator
16 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
SOSCO
SOSCI
FVR
FVR
FVR
DAC
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
PORTA
RA0:RA7
PORTB
RB0:RB7
PORTC
RC0:RC3
PORTD
RD0:RD7
Timer3
SR Latch
C1/C2
CCP2
PORTE
RE0:RE2
RE3
(1)
DAC
RC6:RC7
DAC