Datasheet

 2012 Microchip Technology Inc. DS30684A-page 133
PIC18(L)F2X/45K50
TABLE 10-1: REGISTERS ASSOCIATED WITH INTERRUPTS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 155
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120
INTCON2 R
BPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —IOCIP121
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 122
IOCB IOCB7 IOCB6 IOCB5 IOCB4
— — — — 158
IOCC IOCC7 IOCC6 IOCC5 IOCC4 — IOCC2 IOCC1 IOCC0 158
IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 130
IPR3
— — — — CTMUIP USBIP TMR3GIP TMR1GIP 131
PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 126
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 127
PIE3
— — — — CTMUIE USBIE TMR3GIE TMR1GIE 128
PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 123
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 124
PIR3
— — — — CTMUIF USBIF TMR3GIF TMR1GIF 125
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 153
RCON IPEN
SBOREN — RI TO PD POR BOR 68
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for interrupts.
TABLE 10-2: CONFIGURATION REGISTERS ASSOCIATED WITH INTERRUPTS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on page
CONFIG3H
MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 391
CONFIG4L DEBUG XINST ICPRT — — LVP — STRVEN 392
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for interrupts.