Datasheet

 2012 Microchip Technology Inc. DS30684A-page 131
PIC18(L)F2X/45K50
REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
— — — — CTMUIP USBIP TMR3GIP TMR1GIP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3 CTMUIP: CTMU Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 USBIP: USB Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR3GIP: TMR3 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR1GIP: TMR1 Gate Interrupt Priority bit
1 = High priority
0 = Low priority