Datasheet

 2012 Microchip Technology Inc. DS30684A-page 119
PIC18(L)F2X/45K50
10.4 INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
10.5 PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request Flag registers (PIR1, PIR2 and PIR3).
10.6 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2 and PIE3). When
IPEN = 0, the PEIE/GIEL bit must be set to enable any
of these peripheral interrupts.
10.7 IPR Registers
The IPR registers contain the individual priority bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Priority registers (IPR1, IPR2 and IPR3). Using the priority
bits requires that the Interrupt Priority Enable (IPEN) bit be
set.