PIC18(L)F2X/45K50 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology Universal Serial Bus Features: • USB V2.0 Compliant • Crystal-less Full Speed (12 Mb/s) and Low-Speed Operation (1.
10-Bit A/D Channels Comparators CCP/ ECCP BOR/LVD CTMU MSSP EUSART Timers 8-bit/16-bit USB 2.
PIC18(L)F2X/45K50 Pin Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 RE0 RE1 RE2 VDD VSS RA7 RA6 RC0 RC1 RC2 VUSB3V3 RD0 RD1 PIC18(L)F45K50 40-PIN PDIP (600 MIL) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 D+ DRD3 RD2 Pin Diagram 40 39 38 37 36 35 34 33 32 31 RC6 D+ DRD3 RD2 RD1 RD0 VUSB3V3 RC2 RC1 40-PIN UQFN 1 2 3 4 5 6 7 8 9 10 PIC18(L)F45K50 30 RC0 29 RA6 28 RA7 27
PIC18(L)F2X/45K50 Pin Diagram PIC18(L)F45K50 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC/ICRST(1)/ICVPP(1) RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 NC/ICCK(1)/ICPGC(1) NC/ICDT(1)/ICPGD(1) RB4 RB5 RB6 RB7 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 44 43 42 41 40 39 38 37 36 35 34 RC6 D+ DRD3 RD2 RD1 RD0 VUSB3V3 RC2 RC1 NC 44-PIN TQFP Note 1: Special ICPORT programming/debug port features available when ICPRT = 1 DS3068
2 5 20 22 AN3 6 3 6 21 23 RA5 7 4 7 22 24 RA6 10 7 14 29 31 OSC2 CLKO RA7 9 6 13 28 30 OSC1 CLKI RB0 21 18 33 8 8 AN12 RB1 22 19 34 9 9 AN10 RB2 23 20 35 10 10 AN8 RB3 24 21 36 11 11 AN9 RB4 25 22 37 12 14 AN11 RB5 26 23 38 13 15 AN13 RB6 27 24 39 14 RB7 28 25 40 15 AN4 CTMU C2IN+ VREFDACOUT C1IN+ VREF+ C1OUT SRQ C2OUT SRNQ SRI C12IN3- C12IN2- T0CKI HLVDIN SS FLT0 SDI SDA INT0 Y P1C(5) SCK SCL INT1 Y CTED
RC1 12 9 16 31 35 RC2 13 10 17 32 36 CCP2 AN14 CTPLS SOSCI CCP1 P1A 14 11 18 33 37 — VUSB3V3 — 15 12 23 38 42 — DD+ IOCC1 IOCC2 VDDCORE IOCC4 — 16 13 24 39 43 — RC6 17 14 25 40 44 AN18 TX CK IOCC5 RC7 18 15 26 1 1 AN19 RX DT RD0 — — 19 34 38 AN20 RD1 — — 20 35 39 AN21 RD2 — — 21 36 40 AN22 2012 Microchip Technology Inc.
18 — 20 17 11, 32 7, 26 7, 28 VDD 8, 19 5, 16 12, 31 6, 27 6, 29 VSS – –- 12(3) ICPGC(3) ICCK(3) –- 13 (3) (3) ICDT(3) –- 33(3) – –- Alternate CCP2 pin location based on Configuration bit. Alternate T3CKI pin location based on Configuration bits. Pins are enabled when ICPRT = 1, otherwise, they are disabled. Location on 40/44-Pin parts (PIC18(L)F45K50). Function not on this pin on 28-Pin parts (PIC18(L)F2XK50). Location on 28-Pin parts (PIC18(L)F2XK50).
PIC18(L)F2X/45K50 Table of Contents 1.0 Device Overview ....................................................................................................................................................................... 13 2.0 Guidelines for Getting Started with PIC18(L)F2X/45K50 Microcontrollers ................................................................................ 27 3.0 Oscillator Module (With Fail-Safe Clock Monitor)..........................................................................
PIC18(L)F2X/45K50 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC18(L)F2X/45K50 NOTES: DS30684A-page 10 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18(L)F45K50 • PIC18(L)F25K50 • PIC18(L)F24K50 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Flash program memory.
PIC18(L)F2X/45K50 1.2 Other Special Features • Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 10K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-programmability: These devices can write to their own program memory spaces under internal software control.
PIC18(L)F2X/45K50 TABLE 1-1: DEVICE FEATURES Features PIC18(L)F24K50 PIC18(L)F25K50 PIC18(L)F45K50 Program Memory (Bytes) 16384 32768 32768 Program Memory (Instructions) 8192 16384 16384 Data Memory (Bytes) 2048 2048 2048 Data EEPROM Memory (Bytes) 256 256 (1) I/O Ports A, B, C, E Capture/Compare/PWM Modules (CCP) Enhanced CCP Modules (ECCP) 10-bit Analog-to-Digital Module (ADC) Packages 1 256 (1) A, B, C, E 1 1 1 1 3 internal 14 input 3 internal 14 input 3 internal 25 input
PIC18(L)F2X/45K50 FIGURE 1-1: PIC18(L)F2X/45K50 FAMILY BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Latch 8 8 inc/dec logic Data Memory PCLATU PCLATH 21 PORTA Address Latch 20 PCU PCH PCL Program Counter RA0:RA7 12 Data Address<12> 31-Level Stack 4 BSR Address Latch Program Memory (16/32 Kbytes) STKPTR 12 FSR0 FSR1 FSR2 Data Latch 8 4 Access Bank PORTB 12 RB0:RB7 inc/dec logic Table Latch Address Decode ROM Latch Instruction Bus <16> PORTC RC0:RC3 RC6:RC7 IR Instruction Deco
PIC18(L)F2X/45K50 TABLE 1-2: PIC18(L)F2XK50 PINOUT I/O DESCRIPTIONS Pin Number PDIP, SOIC, SSOP QFN 2 27 3 4 5 6 7 10 Legend: Note 1: 2: Pin Name 28 1 2 3 4 7 Pin Type Buffer Type Description RA0/C12IN0-/AN0 RA0 I/O TTL/DIG C12IN0- I Analog Comparators C1 and C2 inverting input. Digital I/O. AN0 I Analog Analog input 0. RA1/C12IN1-/AN1 RA1 I/O TTL/DIG C12IN1- I Analog Comparators C1 and C2 inverting input. Digital I/O. AN1 I Analog Analog input 1.
PIC18(L)F2X/45K50 TABLE 1-2: PIC18(L)F2XK50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP, SOIC, SSOP QFN 9 6 21 22 23 24 Pin Type Buffer Type RA7 I/O TTL/DIG CLKI I CMOS External clock source input. Always associated with pin function OSC1. OSC1 I ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. Pin Name 18 19 20 21 RA7/CLKI/OSC1 Note 1: 2: Digital I/O.
PIC18(L)F2X/45K50 TABLE 1-2: PIC18(L)F2XK50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP, SOIC, SSOP QFN 25 22 Pin Name 27 28 11 12 Legend: Note 1: 2: 23 24 25 8 9 Buffer Type I/O TTL/DIG Description RB4/IOCB4/P1D/AN11 RB4 26 Pin Type Digital Output or Input with internal pull-up option. IOCB4 I TTL Interrupt-on-change pin. P1D O DIG Enhanced CCP1 PWM output. AN11 I Analog Analog input 11.
PIC18(L)F2X/45K50 TABLE 1-2: PIC18(L)F2XK50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP, SOIC, SSOP QFN 13 10 Pin Name 15 16 17 18 1 11 12 13 14 15 26 Buffer Type I/O ST/DIG Description RC2/CTPLS/P1A/CCP1/IOCC2/AN14 RC2 14 Pin Type Digital I/O. CTPLS O DIG CTMU pulse generator output. P1A O DIG Enhanced CCP1 PWM output. CCP1 I/O ST/DIG IOCC2 I TTL AN14 I Analog VUSB3V3 P — Capture 1 input/Compare 1 output/PWM 1 output. Interrupt-on-change pin.
PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP TQFP UQFN 2 19 17 3 4 5 6 7 14 13 20 21 22 23 24 31 30 19 20 21 22 29 28 Buffer Type Description RA0/C12IN0-/AN0 RA0 I/O TTL/DIG Digital I/O. C12IN0- I Analog Comparators C1 and C2 inverting input. AN0 I Analog Analog input 0. RA1/C12IN1-/AN1 RA1 I/O TTL/DIG Digital I/O. C12IN1- I Analog Comparators C1 and C2 inverting input. AN1 I Analog Analog input 1.
PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP UQFN 33 8 8 34 9 9 36 37 38 10 11 14 15 11 12 13 Description RB0 I/O TTL/DIG Digital Output or Input with internal pull-up option. INT0 I ST FLT0 I ST PWM Fault input for ECCP auto-shutdown. SDI I ST SPI Data in (MSSP). SDA I/O I2C™ SRI I ST AN12 I Analog External interrupt 0. I2C™ Data I/O (MSSP). SR latch input. Analog input 12.
PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP UQFN 39 16 14 17 15 16 17 32 35 36 30 31 32 23 24 37 42 43 38 39 TTL/DIG Digital Output or Input with internal pull-up option. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/IOCB7/PGD I/O TTL/DIG Digital Output or Input with internal pull-up option. IOCB7 I TTL Interrupt-on-change pin.
PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP UQFN 25 44 40 1 1 20 21 22 27 28 29 30 38 39 40 41 35 36 37 2 2 3 3 4 4 5 ST/DIG 5 Digital I/O. IOCC6 I TTL TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). AN18 I Analog Interrupt-on-change pin. Analog input 18. RC7/RX/DT/SDO/IOCC7/AN19 RC7 I/O ST/DIG RX I ST EUSART asynchronous receive.
PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type RE0 I/O ST/DIG Digital I/O. AN5 I Analog Analog input 5. RE1 I/O ST/DIG Digital I/O. AN6 I Analog Analog input 6. Pin Name PDIP TQFP UQFN 8 25 23 9 26 10 24 27 1 25 18 — 16 12 — — 13 — RE0/AN5 RE1/AN6 RE2/AN7 RE2 I/O ST AN7 I Analog RE3 I ST VPP P MCLR I ST Active-low Master Clear (device Reset) input.
PIC18(L)F2X/45K50 NOTES: DS30684A-page 24 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 Getting started with the PIC18(L)F2X/45K50 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. C2(2) VDD R1 R2 MCLR These pins must also be connected if they are being used in the end application: • PGC/PGD pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when an external oscillator source is used (see Section 2.
PIC18(L)F2X/45K50 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD and VSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC18(L)F2X/45K50 Voltage Regulator Pins (VUSB3V3) The on-chip voltage regulator must always be connected directly to either a supply voltage or to an external capacitor. When the regulator is enabled (F devices), a low-ESR (< 5Ω) capacitor is required on the VUSB3V3 pin to stabilize the voltage regulator output voltage. The VUSB3V3 pin must not be connected to VDD and is recommended to use a ceramic capacitor of between 0.22 to 0.47 µF connected to ground.
PIC18(L)F2X/45K50 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100Ω.
PIC18(L)F2X/45K50 FIGURE 2-4: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Single-Sided and In-Line Layouts: Copper Pour (tied to ground) Primary Oscillator Crystal DEVICE PINS Primary Oscillator OSC1 C1 ` OSC2 GND C2 ` SOSCO SOSCI Timer1 Oscillator Crystal ` T1 Oscillator: C1 T1 Oscillator: C2 Fine-Pitch (Dual-Sided) Layouts: Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 Oscillator Crystal GND C1 OSCI DEVICE PINS 2012 Microchip Technology Inc
PIC18(L)F2X/45K50 NOTES: DS30684A-page 30 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 3.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 3.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits.
PIC18(L)F2X/45K50 FIGURE 3-1: SIMPLIFIED OSCILLATOR SYSTEM BLOCK DIAGRAM Secondary Oscillator(1) SOSCO Secondary Oscillator (SOSC) SOSCI Low-Power Mode Event Switch (SCS<1:0>) SOSCOUT 2 Primary Clock Module Secondary Oscillator PCLKEN PRISD PLL_Select EN IDLE (4) CPU FOSC<3:0> Primary Oscillator INTOSC 6 3x or 4xPLL 0 0 1 1 PLL Postscaler Primary Oscillator(2) ( OSC) OSC1 01 4 3 2 11 Primary Clock 10 00 01 00 Clock Switch MUX OSC2 CPUDIV (3) Peripherals RA6 4 CLKO E
PIC18(L)F2X/45K50 3.2 Oscillator Control The OSCCON, OSCCON2 and OSCTUNE registers (Register 3-1 to Register 3-3) control several aspects of the device clock’s operation, both in full-power operation and in power-managed modes.
PIC18(L)F2X/45K50 FIGURE 3-2: INTERNAL OSCILLATOR MUX BLOCK DIAGRAM IRCF<2:0> INTSRC 3 HF-16 MHz HF-8 MHz HF-4 MHz HF-2 MHz HF-1 MHz HF-500 kHz HF-250 kHz 111 110 101 100 011 010 001 INTOSC HF-31.25 kHz 1 LF-31.25 kHz TABLE 3-1: 31.
PIC18(L)F2X/45K50 3.
PIC18(L)F2X/45K50 REGISTER 3-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 R-0/0 R-0/q R/W-0 R/W-0/0 R/W-0/u R/W-1/1 R-0/0 R-0/0 PLLRDY SOSCRUN INTSRC PLLEN SOSCGO(1) PRISD HFIOFR LFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown q = depends on condition -n/n = Value at POR and BOR/Value at all other Resets bit 7 PLLRDY: PLL Run Status bit 1 = System clock comes from PLL 0 = System
PIC18(L)F2X/45K50 3.4 Clock Source Modes Clock source modes can be classified as external or internal. External Clock Modes 3.5.1 OSCILLATOR START-UP TIMER (OST) When the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep.
PIC18(L)F2X/45K50 3.5.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-5). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes.
PIC18(L)F2X/45K50 3.5.4 EXTERNAL RC MODES 3.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. 3.5.4.1 FIGURE 3-7: EXTERNAL RC MODES VDD PIC® MCU REXT OSC1/CLKIN Internal Clock CEXT VSS FOSC/4 or I/O(2) OSC2/CLKO(1) Recommended values: 10 k REXT 100 k CEXT > 20 pF Note 1: 2: 3.5.4.
PIC18(L)F2X/45K50 3.6.1.1 OSCTUNE Register The OSCTUNE register also implements the SPLLMULT bit, which controls whether 3x or 4xPLL clock multiplication is used when the PLL is enabled dynamically in software. For more details about the function of the SPLLMULT bit see Section 3.8.2 “PLL in HFINTOSC Modes”. The HFINTOSC oscillator circuits are factory calibrated but can be adjusted in software by writing to the TUN<6:0> bits of the OSCTUNE register (Register 33).
PIC18(L)F2X/45K50 3.7.1 INTRC The Low-Frequency Internal Oscillator (INTRC) is a 31.25 kHz internal clock source. The INTRC is not tunable, but is designed to be stable across temperature and voltage. See Section 29.0 “Electrical Characteristics” for the INTRC accuracy specifications. The output of the INTRC can be a clock source to the primary clock or the INTOSC clock (see Figure 3-1).
PIC18(L)F2X/45K50 3.8 PLL Frequency Multiplier A Phase-Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from the crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. 3.8.
PIC18(L)F2X/45K50 3.10 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 5.7 “Device Reset Timers”. The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up.
PIC18(L)F2X/45K50 3.11 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS<1:0>) bits of the OSCCON register. PIC18(L)F2X/45K50 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source.
PIC18(L)F2X/45K50 3.12 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.
PIC18(L)F2X/45K50 3.12.2 1. 2. 3. 4. 5. 6. TWO-SPEED START-UP SEQUENCE 3.12.3 Wake-up from Power-on Reset or Sleep. Instructions begin executing by the internal oscillator at the frequency set in the IRCF<2:0> bits of the OSCCON register. OST enabled to count 1024 external clock cycles. OST timed out. External clock is ready. OSTS is set.
PIC18(L)F2X/45K50 3.13 3.13.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the CONFIG1H Configuration register. The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC, RC and RCIO).
PIC18(L)F2X/45K50 FIGURE 3-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test TABLE 3-4: INTCON IPR2 OSCCON Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
PIC18(L)F2X/45K50 3.14 Oscillator Settings for USB When the PIC18(L)F2X/45K50 family devices are used for USB connectivity, a 6 MHz or 48 MHz clock must be provided to the USB module for operation in either Low-Speed or Full-Speed modes, respectively. This may require some forethought in selecting an oscillator frequency and programming the device. The full range of possible oscillator configurations compatible with USB operation is shown in Table 3-7. 3.14.
PIC18(L)F2X/45K50 3.15 Active Clock Tuning (ACT) Module The Active Clock Tuning (ACT) module continuously adjusts the 16 MHz internal oscillator, using an available external reference, to achieve ± 0.20% accuracy. This eliminates the need for a high-speed, high-accuracy external crystal when the system has an available lower speed, lower power, high-accuracy clock source available.
PIC18(L)F2X/45K50 3.20 Active Clock Tuning Update Disable When the ACT module is enabled, the OSCTUNE register is continuously updated every ACT_clk period. Setting the ACT Update Disable bit can be used to suspend updates to the OSCTUNE register, without disabling the module. If the 16 MHz internal oscillator drifts out of the accuracy range, the ACT Status bits will change and an interrupt can be generated to notify the application.
PIC18(L)F2X/45K50 3.
PIC18(L)F2X/45K50 TABLE 3-8: SUMMARY OF REGISTERS ASSOCIATED WITH ACT SOURCES Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page ACTCON ACTEN ACTUD — ACTSRC ACTLOCK — ACTORS — 52 OSCCON IDLEN OSTS HFIOFS OSCTUNE SPLLMULT OSCCON2 PLLRDY Name IRCF<2:0> SCS<1:0> TUN<6:0> SOSCRUN INTSRC PLLEN SOSCGO 35 40 PRISD HFIOFR LFIOFS 36 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 123 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129
PIC18(L)F2X/45K50 NOTES: DS30684A-page 54 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 4.0 4.1.1 POWER-MANAGED MODES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18(L)F2X/45K50 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).
PIC18(L)F2X/45K50 4.1.3 MULTIPLE FUNCTIONS OF THE SLEEP COMMAND The power-managed mode that is invoked with the SLEEP instruction is determined by the value of the IDLEN bit at the time the instruction is executed. If IDLEN = 0, when SLEEP is executed, the device enters the sleep mode and all clocks stop and minimum power is consumed. If IDLEN = 1, when SLEEP is executed, the device enters the IDLE mode and the system clock continues to supply a clock to the peripherals but is disconnected from the CPU.
PIC18(L)F2X/45K50 On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-3). When the clock switch is complete, the HFIOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch.
PIC18(L)F2X/45K50 TABLE 4-2: INTERNAL OSCILLATOR FREQUENCY STABILITY BITS IRCF<2:0> INTSRC Selected Oscillator Selected Oscillator Stable when: 000 0 INTRC LFIOFS = 1 000 1 HFINTOSC HFIOFS = 1 001-111 x HFINTOSC HFIOFS = 1 FIGURE 4-3: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition(2) CPU Clock Peripheral Clock Program Counter PC + 2 PC SCS<1:0> bits Change
PIC18(L)F2X/45K50 4.3 Sleep Mode The Power-Managed Sleep mode in the PIC18(L)F2X/ 45K50 devices is identical to the legacy Sleep mode offered in all other PIC® microcontroller devices. It is entered by clearing the IDLEN bit of the OSCCON register and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-4) and all clock source status bits are cleared. Entering the Sleep mode from either Run or Idle mode does not require a clock switch.
PIC18(L)F2X/45K50 4.4 Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out, or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode).
PIC18(L)F2X/45K50 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the SOSC oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS<1:0> bits to ‘01’ and execute SLEEP. When the clock source is switched to the SOSC oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the SOSCRUN bit is set.
PIC18(L)F2X/45K50 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block from the HFINTOSC multiplexer output. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP.
PIC18(L)F2X/45K50 4.5.3 EXIT BY RESET Exiting Sleep and Idle modes by Reset causes code execution to restart at address 0. See Section 5.0 “Reset” for more details. The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator. 4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all.
PIC18(L)F2X/45K50 4.7 Register Definitions: Peripheral Module Disable REGISTER 4-2: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’.
PIC18(L)F2X/45K50 REGISTER 4-3: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 MSSPMD: MSSP Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, mod
PIC18(L)F2X/45K50 NOTES: DS30684A-page 66 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 5.0 RESET The PIC18(L)F2X/45K50 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers.
PIC18(L)F2X/45K50 5.
PIC18(L)F2X/45K50 5.3 Master Clear (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. An internal weak pull-up is enabled when the pin is configured as the MCLR input. FIGURE 5-2: In PIC18(L)F2X/45K50 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input.
PIC18(L)F2X/45K50 5.5 Brown-out Reset (BOR) PIC18(L)F2X/45K50 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV<1:0> and BOREN<1:0> bits of the CONFIG2L Configuration register. There are a total of four BOR configurations which are summarized in Table 5-1. The BOR threshold is set by the BORV<1:0> bits.
PIC18(L)F2X/45K50 TABLE 5-1: BOR CONFIGURATIONS BOR Configuration Status of SBOREN (RCON<6>) BOR Operation BOREN1 BOREN0 0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR enabled by software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled by hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled by hardware; must be disabled by reprogramming the Configuration bits. 5.
PIC18(L)F2X/45K50 TABLE 5-2: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration HSPLL Power-up(2) and Brown-out PWRTEN = 1 Exit from Power-Managed Mode 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) PWRTEN = 0 66 ms (1) + 1024 TOSC + 2 ms(2) 66 ms(1) + 1024 TOSC HS, XT, LP 1024 TOSC 1024 TOSC EC, ECIO (1) 66 ms — — RC, RCIO 66 ms(1) — — (1) — — INTOSC, INTOSCIO 66 ms Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
PIC18(L)F2X/45K50 FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 FIGURE 5-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. DS30684A-page 74 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 5.8 Table 6-2 describes the Reset states for all of the Special Function Registers. The table identifies differences between Power-On Reset (POR)/BrownOut Reset (BOR) and all other Resets, (i.e., Master Clear, WDT Resets, STKFUL, STKUNF, etc.). Additionally, the table identifies register bits that are changed when the device receives a wake-up from WDT or other interrupts. Reset State of Registers Some registers are unaffected by a Reset.
PIC18(L)F2X/45K50 TABLE 5-5: CONFIGURATION REGISTERS ASSOCIATED WITH RESETS Bit 7 Bit 6 Bit 5 CONFIG2L — — LPBOR — — CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 391 CONFIG4L DEBUG XINST ICPRT — — LVP — STRVEN 392 CONFIG2H Bit 4 Bit 3 BORV<1:0> WDTPS<3:0> Bit 2 Bit 1 Bit 0 Register on page Name BOREN<1:0> PWRTEN WDTEN<1:0> 389 390 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets. DS30684A-page 76 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 6.0 MEMORY ORGANIZATION 6.1 PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction).
PIC18(L)F2X/45K50 6.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18(L)F2X/45K50 6.1.2.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (stack full) Status bit and the STKUNF (Stack Underflow) Status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value.
PIC18(L)F2X/45K50 6.1.2.3 PUSH and POP Instructions The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature.
PIC18(L)F2X/45K50 EXAMPLE 6-1: FAST REGISTER STACK CODE EXAMPLE CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK RETURN, FAST SUB1 6.2.3 ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK LOOK-UP TABLES IN PROGRAM MEMORY 6.2.3.2 Table Reads and Table Writes A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes.
PIC18(L)F2X/45K50 6.3 6.3.2 PIC18 Instruction Cycle 6.3.1 An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18(L)F2X/45K50 6.3.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as either two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of two and the LSb will always read ‘0’ (see Section 6.1.1 “Program Counter”).
PIC18(L)F2X/45K50 6.4 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.7 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each.
PIC18(L)F2X/45K50 FIGURE 6-5: DATA MEMORY MAP FOR PIC18(L)F2X/45K50 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When ‘a’ = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 GPR FFh 00h 2FFh 300h When ‘a’ = 1: The BSR specifies the Bank used by the instruction.
PIC18(L)F2X/45K50 FIGURE 6-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 Bank Select(2) 0 0 0 1 1 000h Data Memory Bank 0 100h Bank 1 200h 300h Bank 2 00h 7 FFh 00h 1 From Opcode(2) 1 1 1 1 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank.
PIC18(L)F2X/45K50 6.4.3 ACCESS BANK While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient.
PIC18(L)F2X/45K50 TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F2X/45K50 DEVICES Address Name Address Name Address FFFh TOSU FD7h TMR0H FAFh FFEh TOSH FD6h TMR0L FFDh TOSL FD5h FFCh STKPTR FD4h Name Address Name Address Name SPBRG1 F87h IOCC F5Fh ANSELE(3) FAEh RCREG1 F86h IOCB F5Eh ANSELD(3) T0CON FADh TXREG1 F85h WPUB F5Dh ANSELC —(2) FACh TXSTA1 F84h PORTE F5Ch ANSELB F5Bh ANSELA F5Ah VREGCON(4) FFBh PCLATU FD3h OSCCON FABh RCSTA1 F83h
PIC18(L)F2X/45K50 TABLE 6-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/45K50 DEVICES Name Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Top-of-Stack, Upper Byte (TOS<20:16>) Value on POR, BOR FFFh TOSU FFEh TOSH Top-of-Stack, High Byte (TOS<15:8>) FFDh TOSL Top-of-Stack, Low Byte (TOS<7:0>) FFCh STKPTR STKFUL STKUNF — STKPTR<4:0> 00-0 0000 FFBh PCLATU — — — Holding Register for PC<20:16> ---0 0000 FFAh PCLATH Holding Register for PC<15:8> FF9h PCL Holdi
PIC18(L)F2X/45K50 TABLE 6-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/45K50 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR FCFh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx FCEh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx FCDh T1CON FCCh T1GCON SOSCEN T1SYNC TMR1GE TMR1CS<1:0> T1GPOL T1GTM T1CKPS<1:0> T1GSPM T1GGO/ DONE T1GVAL FCBh SS
PIC18(L)F2X/45K50 TABLE 6-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/45K50 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR F9Fh IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 F9Eh PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 F9Dh PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 F9Ch HLVDCON VDIRMAG BGVST IRVST HLVDEN F9Bh OSCTUNE SPLLMULT F9Ah CM2CON1 MC1OU
PIC18(L)F2X/45K50 TABLE 6-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/45K50 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR F6Fh UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Eh UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Dh UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Ch UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Bh UEP1 — — — EPH
PIC18(L)F2X/45K50 6.4.6 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed.
PIC18(L)F2X/45K50 6.6 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.7 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18(L)F2X/45K50 6.6.3.1 FSR Registers and the INDF Operand 6.6.3.2 At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. Each FSR pair holds a 12-bit value, therefore, the four upper bits of the FSRnH register are not used. The 12-bit FSR value can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations.
PIC18(L)F2X/45K50 Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of indexed addressing in the data memory space.
PIC18(L)F2X/45K50 FIGURE 6-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When ‘a’ = 0 and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 60h are not available in this addressing mode.
PIC18(L)F2X/45K50 6.7.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom section of Bank 0, this mode maps the contents from a user defined “window” that can be located anywhere in the data memory space.
PIC18(L)F2X/45K50 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the specified VDD ranges. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time.
PIC18(L)F2X/45K50 FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Holding Registers Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL actually point to an address within the write block holding registers. The MSBs of the Table Pointer determine where the write block will eventually be written.
PIC18(L)F2X/45K50 7.
PIC18(L)F2X/45K50 7.3.1 TABLAT – TABLE LATCH REGISTER When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory directly into the TABLAT register. The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.3.
PIC18(L)F2X/45K50 7.4 Reading the Flash Program Memory The TBLRD instruction retrieves data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 7-4 shows the interface between the internal program memory and the TABLAT. TBLPTR points to a byte address in program space.
PIC18(L)F2X/45K50 7.5 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP™ control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. The TBLPTR<5:0> bits are ignored.
PIC18(L)F2X/45K50 The programming block size is 64 bytes. Word or byte programming is not supported. The long write is necessary for programming the internal Flash. Instruction execution is halted during a long write cycle. The long write will be terminated by the internal programming timer. Table writes are used internally to load the holding registers needed to program the Flash memory. There are only as many holding registers as there are bytes in a write block (64 bytes).
PIC18(L)F2X/45K50 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64’ COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; poi
PIC18(L)F2X/45K50 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) DECFSZ BRA COUNTER WRITE_WORD_TO_HREGS ; loop until holding registers are full BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF DCFSZ BRA BSF BCF EECON1, EEPGD EECON1, CFGS EECON1, WREN INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR COUNTER2 WRITE_BYTE_TO_HREGS INTCON, GIE EECON1, WREN ; ; ; ; PROGRAM_MEMORY Required Sequence 7.6.
PIC18(L)F2X/45K50 NOTES: DS30684A-page 108 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 8.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, which is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the specified VDD range.
PIC18(L)F2X/45K50 REGISTER 8-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memo
PIC18(L)F2X/45K50 8.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register and then set control bit, RD. The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).
PIC18(L)F2X/45K50 8.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 26.0 “Special Features of the CPU” for additional information. 8.
PIC18(L)F2X/45K50 TABLE 8-1: Name REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL EEADR EEADR7 EEADR6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 — EEDATA EEPROM Data Register — EECON2 EEPROM Control Register 2 (not a physical register) — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 110 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP C
PIC18(L)F2X/45K50 NOTES: DS30684A-page 114 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle.
PIC18(L)F2X/45K50 Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES<3:0>).
PIC18(L)F2X/45K50 10.0 INTERRUPTS The PIC18(L)F2X/45K50 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high or low priority level (INT0 does not have a priority bit, it is always a high priority). The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. A high priority interrupt event will interrupt a low priority interrupt that may be in progress.
PIC18(L)F2X/45K50 Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.
PIC18(L)F2X/45K50 10.4 INTCON Registers The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. 10.5 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request Flag registers (PIR1, PIR2 and PIR3). 10.6 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts.
PIC18(L)F2X/45K50 10.
PIC18(L)F2X/45K50 REGISTER 10-2: INTCON2: INTERRUPT CONTROL 2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled provided that the pin is an input and the corresponding
PIC18(L)F2X/45K50 REGISTER 10-3: INTCON3: INTERRUPT CONTROL 3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0
PIC18(L)F2X/45K50 REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ACTIF: Active Clock Tuning Interrupt Flag bit 1 = An Active Clock Tuning Event generated an interrupt (must be cleared in software) 0 =
PIC18(L)F2X/45K50 REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by so
PIC18(L)F2X/45K50 REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT (FLAG) REGISTER 3 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CTMUIF USBIF TMR3GIF TMR1GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 CTMUIF: CTMU Interrupt Flag bit 1 = CTMU interrupt occurred (must be cleared in software) 0 = No CTMU interrupt occurred bit 2 USBIF: USB In
PIC18(L)F2X/45K50 REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACTIE: Active Clock Tuning Interrupt Enable bit 1 = Enables Active Clock Tuning interrupt 0 = Disables Active Clock Tuning interrupt bit 6 ADIE: A/D Co
PIC18(L)F2X/45K50 REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 C1IE: Comparator C1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5
PIC18(L)F2X/45K50 REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 3 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CTMUIE USBIE TMR3GIE TMR1GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 CTMUIE: CTMU Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 USBIE: USB Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR
PIC18(L)F2X/45K50 REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACTIP: Active Clock Tuning Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = L
PIC18(L)F2X/45K50 REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 C1IP: Comparator C1 Interrupt Priority bit 1 = High priority 0 = Low
PIC18(L)F2X/45K50 REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — CTMUIP USBIP TMR3GIP TMR1GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 CTMUIP: CTMU Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 USBIP: USB Interrupt Priority bit 1 = High priority 0 = Low pr
PIC18(L)F2X/45K50 10.9 INTn Pin Interrupts 10.10 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE.
PIC18(L)F2X/45K50 TABLE 10-1: Name ANSELB INTCON REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 — — GIE/GIEH PEIE/GIEL INTCON2 RBPU INTEDG0 INTCON3 INT2IP INT1IP Bit 2 Bit 1 Bit 0 Register on page ANSB3 ANSB2 ANSB1 ANSB0 155 IOCIE TMR0IF INT0IF IOCIF 120 Bit 5 Bit 4 Bit 3 ANSB5 ANSB4 TMR0IE INT0IE INTEDG1 INTEDG2 — — TMR0IP — IOCIP 121 INT2IE INT1IE — INT2IF INT1IF 122 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 158 IOCC IOCC7 IOCC6 IOCC5 IOCC4 — IOCC2
PIC18(L)F2X/45K50 NOTES: DS30684A-page 134 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 11.0 I/O PORTS 11.1 Depending on the device selected and features enabled, there are up to five ports available. All pins of the I/O ports are multiplexed with one or more alternate functions from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has five registers for its operation.
PIC18(L)F2X/45K50 TABLE 11-1: PORTA I/O SUMMARY Pin Name Function RA0/C12IN0-/AN0 RA0 RA1/C12IN1-/AN1 RA2/C2IN+/AN2/ DACOUT/VREF- RA3/C1IN+/AN3/ VREF+ RA4/C1OUT/SRQ/ T0CKI RA5/C2OUT/ SRNQ/SS1/ HLVDIN/AN4 RA6/CLKO/OSC2 Legend: TRIS ANSEL Setting Setting Pin Type Buffer Type Description 0 x O DIG LATA<0> data output; not affected by analog input. 1 0 I TTL PORTA<0> data input; disabled when analog input enabled. C12IN0- 1 1 I AN Comparators C1 and C2 inverting input.
PIC18(L)F2X/45K50 TABLE 11-1: PORTA I/O SUMMARY (CONTINUED) Pin Name RA7/CLKI/OSC1 Legend: TRIS ANSEL Setting Setting Function RA7 Pin Type Buffer Type Description 0 — O DIG LATA<7> data output; disabled in external oscillator modes. 1 — I TTL PORTA<7> data input; disabled in external oscillator modes. CLKI x — I AN External clock source input; always associated with pin function OSC1.
PIC18(L)F2X/45K50 11.1.1 PORTA OUTPUT PRIORITY Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table 11-4 lists the PORTA pin functions from the highest to the lowest priority.
PIC18(L)F2X/45K50 TABLE 11-4: PORT PIN FUNCTION PRIORITY Port Function Priority by Port Pin Port bit 0 PORTA PORTB PORTC RA0 SDA SOSCO PORTD(2) PORTE(2) RD0 RE0 RB0 RC0 1 RA1 SCL SOSCI SCK CCP2(3) (1) RB1 2 DACOUT RA2 RE1 RD1 P1C RC1 CCP1 P1B(1) P1A RB2 CTPLS RD2 RE2 RC2 3 RA3 SDO(3) MCLR CCP2(4) RD3 VPP RE3 RB3 4 SRQ P1D(1) C1OUT RB4 DRD4 RA4 5 SRNQ D+ C2OUT P1B RD5 RA5 RB5 6 OSC2 PGC TX/CK CLKO ICDCK P1C RA6 RB6 RD6 OSC1 PGD RA7 ICDDT RC6 7 R
PIC18(L)F2X/45K50 11.2 PORTB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped.
PIC18(L)F2X/45K50 11.3.3 A mismatch condition will continue to set the IOCIF flag bit. Reading or writing PORTB will end the mismatch condition and allow the IOCIF bit to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After either one of these Resets, the IOCIF flag will continue to be set if a mismatch is present. PORTB is multiplexed with several peripheral functions (Table 11-5). The pins have TTL input buffers.
PIC18(L)F2X/45K50 TABLE 11-5: PORTB I/O SUMMARY (CONTINUED) Pin Function RB2/INT2/CTED1/ P1B/AN8 RB2 RB3/CTED2/CCP2/ SDO/C12IN2-/AN9 RB4/IOCB4/P1D/ AN11 RB5/IOCB5/T3CKI/ T1G/AN13 RB6/IOCB6/PGC RB7/IOCB7/PGD Legend: Note 1: 2: 3: TRIS ANSEL Setting Setting Pin Type Buffer Type Description 0 x O DIG LATB<2> data output; not affected by analog input. 1 0 I TTL PORTB<2> data input; disabled when analog input enabled. External interrupt 2.
PIC18(L)F2X/45K50 TABLE 11-6: Name ANSELB ECCP1AS REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 — — ECCP1ASE CCP1CON Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 ECCP1AS<2:0> P1M<1:0> PSS1AC<1:0> PSS1BD<1:0> DC1B<1:0> CCP1M<3:0> DC2B<1:0> CCP2M<3:0> Register on page 155 210 206 — — INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP 121 INTCON3 INT2IP INT1IP —
PIC18(L)F2X/45K50 11.4 PORTC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., disable the output driver). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped.
PIC18(L)F2X/45K50 TABLE 11-8: PORTC I/O SUMMARY Pin Name RC0/IOCC0/T3CKI/ T3G/T1CKI/SOSCO Function TRIS Setting ANSEL setting Pin Type Buffer Type Description RC0 0 — O DIG LATC<0> data output; not affected by analog input. 1 — I ST PORTC<0> data input; disabled when analog input enabled. 1 — I TTL Interrupt-on-change pin. T3CKI(1) 1 — I ST Timer3 clock input. T3G 1 — I ST Timer3 external clock gate input.
PIC18(L)F2X/45K50 TABLE 11-8: PORTC I/O SUMMARY (CONTINUED) Pin Name RC6/IOCC6/TX/CK/ AN18 Function TRIS Setting ANSEL setting Pin Type Buffer Type Description RC6 0 0 O DIG LATC<6> data output; not affected by analog input. 1 0 I ST PORTC<6> data input; disabled when analog input enabled. 1 0 I TTL Interrupt-on-change pin. IOCC6 RC7/IOCC7/SDO/RX/ DT/AN19 Legend: Note 1: 2: 3: TX 1 0 O DIG EUSART asynchronous transmit data output.
PIC18(L)F2X/45K50 TABLE 11-9: Name ANSELC ECCP1AS REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 ANSC7 ANSC6 ECCP1ASE CCP1CON Bit 5 Bit 4 Bit 3 Bit 2 — — — ANSC2 ECCP1AS<2:0> P1M<1:0> Bit 1 Bit 0 Register on page — — 155 PSS1AC<1:0> PSS1BD<1:0> DC1B<1:0> CCP1M<3:0> DC2B<1:0> CCP2M<3:0> 206 — — CTMUEN — CTMUSIDL TGEN EDGEN LATC7 LATC6 — — — PORTC RC7 RC6 — — — RC2 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB WCOL SSP
PIC18(L)F2X/45K50 11.5 Note: PORTD Registers PORTD is only available on 40-pin and 44-pin devices. PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., disable the output driver). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC18(L)F2X/45K50 TABLE 11-11: PORTD I/O SUMMARY Pin Name RD0/AN20 RD0 RD1/AN21 RD2/AN22 RD3/AN23 RD4/AN24 RD5/P1B/AN25 RD6/P1C/AN26 RD7/P1D/AN27 Legend: Function TRIS ANSEL Pin Buffer Setting setting Type Type Description 0 0 O DIG LATD<0> data output; not affected by analog input. 1 0 I ST PORTD<0> data input; disabled when analog input enabled. AN20 1 1 I AN Analog input 20. RD1 0 0 O DIG LATD<1> data output; not affected by analog input.
PIC18(L)F2X/45K50 TABLE 11-12: REGISTERS ASSOCIATED WITH PORTD Name ANSELD(1) CCP1CON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 155 P1M<1:0> LATD(1) PORTD(1) (1) DC1B<1:0> 206 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 157 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 153 SLRD SLRC SLRB SLRA — — — SLRE SSP1CON1 WCOL SSPOV SSPEN CKP TRISD(1) TRISD7 TRISD6 TRISD5 SLRCON CCP1M<3:0> TRISD4 S
PIC18(L)F2X/45K50 11.6 PORTE Registers Depending on the particular PIC18(L)F2X/45K50 device selected, PORTE is implemented in two different ways. 11.6.1 PORTE ON 40/44-PIN DEVICES For PIC18(L)F2X/45K50 devices, PORTE is a 4-bit wide port. Three pins (RE0/AN5, RE1/AN6 and RE2/ AN7) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘0’s. The corresponding data direction register is TRISE.
PIC18(L)F2X/45K50 TABLE 11-13: PORTE I/O SUMMARY Pin Function RE0/AN5 RE0 RE1/AN6 RE2/AN7 RE3/VPP/MCLR Legend: TRIS ANSEL Pin Setting Setting Type Buffer Type Description 0 0 O DIG LATE<0> data output; not affected by analog input. 1 0 I ST PORTE<0> data input; disabled when analog input enabled. AN5 1 1 I AN Analog input 5. RE1 0 0 O DIG LATE<1> data output; not affected by analog input. 1 0 I ST PORTE<1> data input; disabled when analog input enabled.
PIC18(L)F2X/45K50 11.7 Port Analog Control 11.8 Most port pins are multiplexed with analog functions such as the Analog-to-Digital Converter and comparators. When these I/O pins are to be used as analog inputs it is necessary to disable the digital input buffer to avoid excessive current caused by improper biasing of the digital input. Individual control of the digital input buffers on pins which share analog functions is provided by the ANSELA, ANSELB, ANSELC, ANSELD and ANSELE registers.
PIC18(L)F2X/45K50 REGISTER 11-2: PORTE: PORTE REGISTER U-0 U-0 U-0 U-0 R/W-u/x R/W-u/x R/W-u/x R/W-u/x — — — — RE3(1) RE2(2), (3) RE1(2), (3) RE0(2), (3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-4 Unimplemented: Read as ‘0’ bit 3 RE3: PORTE Input bit value(1) bit 2-0 RE<2:0>: PORTE I/O bit values(2), (3) Note 1: 2
PIC18(L)F2X/45K50 REGISTER 11-4: ANSELB – PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: RB<5:0> Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled REGISTER 11-5: x = Bit is unknown
PIC18(L)F2X/45K50 REGISTER 11-7: ANSELE – PORTE ANALOG SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 — — — — — ANSE2(1) ANSE1(1) ANSE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ANSE<2:0>: RE<2:0> Analog Select bit(1) 1 = Digital input buffer disabled 0 = Digital input buffer enabled Note 1: x = Bit is unknown Available on
PIC18(L)F2X/45K50 REGISTER 11-10: LATx: PORTx OUTPUT LATCH REGISTER(1) R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATx7 LATx6 LATx5 LATx4 LATx3 LATx2 LATx1 LATx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared LATx<7:0>: PORTx Output Latch bit value(2) bit 7-0 Note 1: 2: x = Bit is unknown Register Description for LATA, LATB, LATC and LATD.
PIC18(L)F2X/45K50 REGISTER 11-13: IOCB: INTERRUPT-ON-CHANGE PORTB CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IOCB7 IOCB6 IOCB5 IOCB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 IOCB<7:4>: Interrupt-on-Change PORTB control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unk
PIC18(L)F2X/45K50 REGISTER 11-15: SLRCON: SLEW RATE CONTROL REGISTER U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SLRE(1) SLRD(1) SLRC SLRB SLRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 SLRE: PORTE Slew Rate Control bit(1) 1 = All outputs on PORTE slew at a limited rate 0 = All outputs on PORTE slew at the standard rate bit 3 SLRD: P
PIC18(L)F2X/45K50 NOTES: DS30684A-page 160 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 12.0 The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection. It is both readable and writable.
PIC18(L)F2X/45K50 12.2 Timer0 Operation 12.3 Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit of the T0CON register. In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.4 “Prescaler”). Timer0 incrementing is inhibited for two instruction cycles following a TMR0 register write.
PIC18(L)F2X/45K50 FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 Sync with Internal Clocks 1 Programmable Prescaler T0CKI pin T0SE T0CS 0 TMR0 High Byte TMR0L 8 Set TMR0IF on Overflow (2 TCY Delay) 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: 12.4 Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 12.4.1 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module.
PIC18(L)F2X/45K50 NOTES: DS30684A-page 164 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 13.
PIC18(L)F2X/45K50 13.1 13.2.1 Timer1/3 Operation When the internal clock source is selected the TMRxH:TMRxL register pair will increment on multiples of FOSC as determined by the Timer1/3 prescaler. The Timer1/3 module is a 16-bit incrementing counter which is accessed through the TMRxH:TMRxL register pair. Writes to TMRxH or TMRxL directly update the counter. When the FOSC internal clock source is selected, the Timer1/3 register value will increment by four counts every instruction clock cycle.
PIC18(L)F2X/45K50 13.3 Timer1/3 Prescaler Timer1/3 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The TxCKPS bits of the TxCON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMRxH or TMRxL. 13.4 Secondary Oscillator A dedicated secondary low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output).
PIC18(L)F2X/45K50 FIGURE 13-2: TIMER1/3 16-BIT READ/WRITE MODE BLOCK DIAGRAM From Timer1/3 Circuitry TMR1 High Byte TMR1L 8 Set TMR1IF on Overflow Read TMR1L Write TMR1L 13.7.2 The Timer1/3 gate source can be selected from one of four different sources. Source selection is controlled by the TxGSS bits of the TxGCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the TxGPOL bit of the TxGCON register.
PIC18(L)F2X/45K50 13.7.3 TIMER1/3 GATE TOGGLE MODE When Timer1/3 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1/3 gate signal, as opposed to the duration of a single level pulse. The Timer1/3 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 13-5 for timing details. Timer1/3 Gate Toggle mode is enabled by setting the TxGTM bit of the TxGCON register.
PIC18(L)F2X/45K50 13.8 Timer1/3 Interrupt The Timer1/3 register pair (TMRxH:TMRxL) increments to FFFFh and rolls over to 0000h. When Timer1/3 rolls over, the Timer1/3 interrupt flag bit of the PIR1/2 register is set.
PIC18(L)F2X/45K50 FIGURE 13-3: TIMER1/3 INCREMENTING EDGE TXCKI = 1 when TMRx Enabled TXCKI = 0 when TMRX Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. FIGURE 13-4: TIMER1/3 GATE ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3 N 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 FIGURE 13-5: TIMER1/3 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM TxTxG_IN TxCKI TxGVAL Timer1/3 FIGURE 13-6: N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 TIMER1/3 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL Timer1/3 TMRxGIF DS30684A-page 172 N Cleared by software N+1 N+2 Set by hardware on falling edge of TxGVAL Cleared by software 2012 Microc
PIC18(L)F2X/45K50 FIGURE 13-7: TIMER1/3 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL Timer1/3 TMRxGIF N N+1 Cleared by software N+2 N+3 Set by hardware on falling edge of TxGVAL N+4 Cleared by software 13.
PIC18(L)F2X/45K50 13.
PIC18(L)F2X/45K50 REGISTER 13-2: TxGCON: TIMER1/3 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMRxGE TxGPOL TxGTM TxGSPM TxGGO/DONE TxGVAL R/W-0/u R/W-0/u TxGSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMRxGE: Timer1/3 Gate Enable bi
PIC18(L)F2X/45K50 TABLE 13-5: Name REGISTERS ASSOCIATED WITH TIMER1/3 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 155 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 130 IPR3 — — — — CTMUIP USBIP TMR3GIP TMR1GIP 131 126 PIE1 ACTIE
PIC18(L)F2X/45K50 14.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP module See Figure 14-1 for a block diagram of Timer2.
PIC18(L)F2X/45K50 14.1 Timer2 Operation The clock input to the Timer2 module is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle.
PIC18(L)F2X/45K50 14.
PIC18(L)F2X/45K50 TABLE 14-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 126 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 123 — UARTMD USBMD ACTMD — TMR1MD 64 PMD0 PR2 T2CON TMR2 GIE/GIEH PEIE/GIEL Bit 5 TMR3MD TMR2MD Tim
PIC18(L)F2X/45K50 15.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.
PIC18(L)F2X/45K50 15.1.1 CCP PIN CONFIGURATION In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Some CCPx outputs are multiplexed on a couple of pins. Table 15-1 shows the CCP output pin multiplexing. Selection of the output pin is determined by the CCPxMX bits in Configuration register 3H (CONFIG3H). Refer to Register 26-5 for more details. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition.
PIC18(L)F2X/45K50 15.1.4 CCP PRESCALER There are four prescaler settings specified by the CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt.
PIC18(L)F2X/45K50 TABLE 15-2: Name REGISTERS ASSOCIATED WITH CAPTURE Bit 7 CCP1CON Bit 6 Bit 5 P1M<1:0> CCP2CON — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page DC1B<1:0> CCP1M<3:0> 206 DC2B<1:0> CCP2M<3:0> 206 CCPR1H Capture/Compare/PWM Register 1, High Byte (MSB) — CCPR1L Capture/Compare/PWM Register 1, Low Byte (LSB) — CCPR2H Capture/Compare/PWM Register 2, High Byte (MSB) — CCPR2L Capture/Compare/PWM Register 2, Low Byte (LSB) — — — — — C2TSEL — — C1TSEL 209 G
PIC18(L)F2X/45K50 15.2 15.2.1 Compare Mode The Compare mode function described in this section is identical for all CCP and ECCP modules available on this device family. Compare mode makes use of the 16-bit Timer resources, Timer1 and Timer3. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMRxH:TMRxL register pair.
PIC18(L)F2X/45K50 15.2.4 SPECIAL EVENT TRIGGER When Special Event Trigger mode is selected (CCPxM<3:0> = 1011), and a match of the TMRxH:TMRxL and the CCPRxH:CCPRxL registers occurs, all CCPx and ECCPx modules will immediately: 15.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep.
PIC18(L)F2X/45K50 TABLE 15-4: REGISTERS ASSOCIATED WITH COMPARE Name Bit 7 CCP1CON Bit 6 Bit 5 P1M<1:0> CCP2CON — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page DC1B<1:0> CCP1M<3:0> 206 DC2B<1:0> CCP2M<3:0> 206 CCPR1H Capture/Compare/PWM Register 1, High Byte (MSB) — CCPR1L Capture/Compare/PWM Register 1, Low Byte (LSB) — CCPR2H Capture/Compare/PWM Register 2, High Byte (MSB) — CCPR2L Capture/Compare/PWM Register 2, Low Byte (LSB) — — — — — ADCON1 TRIGSEL — — —
PIC18(L)F2X/45K50 15.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps.
PIC18(L)F2X/45K50 5. 6. Configure and start the 8-bit Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note 1 below. • Configure the T2CKPS bits of the T2CON register with the Timer prescale value. • Enable the Timer by setting the TMR2ON bit of the T2CON register. Enable PWM output pin: • Wait until the Timer overflows and the TMR2IF bit of the PIR1 register is set. See Note 1 below. • Enable the CCPx pin output driver by clearing the associated TRIS bit.
PIC18(L)F2X/45K50 15.3.5 PWM RESOLUTION EQUATION 15-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 15-4.
PIC18(L)F2X/45K50 TABLE 15-9: Name REGISTERS ASSOCIATED WITH STANDARD PWM Bit 7 CCP1CON Bit 6 Bit 5 P1M<1:0> Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page DC1B<1:0> CCP1M<3:0> 206 DC2B<1:0> CCP2M<3:0> 206 CCP2CON — — CCPTMRS — — — — C2TSEL — — C1TSEL 209 GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 130 PIE1 ACTIE ADIE
PIC18(L)F2X/45K50 15.4 To select an Enhanced PWM Output mode, the PxM<1:0> bits of the CCPxCON register must be configured appropriately. PWM (Enhanced Mode) The enhanced PWM function described in this section is available for CCP module ECCP1. The PWM outputs are multiplexed with I/O pins and are designated PxA, PxB, PxC and PxD. The polarity of the PWM pins is configurable and is selected by setting the CCPxM bits in the CCPxCON register appropriately.
PIC18(L)F2X/45K50 TABLE 15-11: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> CCPx/PxA Yes PxC (1) Yes PxD (1) Yes(1) Single 00 Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Yes PxB (1) PWM Steering enables outputs in Single mode.
PIC18(L)F2X/45K50 FIGURE 15-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal PxM<1:0> PRx+1 Pulse Width 0 Period 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay(1) Delay(1) PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:
PIC18(L)F2X/45K50 15.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 15-9). This mode can be used for half-bridge applications, as shown in Figure 15-9, or for full-bridge applications, where four power switches are being modulated with two PWM signals.
PIC18(L)F2X/45K50 15.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of full-bridge application is shown in Figure 15-10. In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be driven to their inactive state as shown in Figure 15-11. In the Reverse mode, PxC is driven to its active state, pin PxB is modulated, while PxA and PxD will be driven to their inactive state as shown Figure 15-11.
PIC18(L)F2X/45K50 FIGURE 15-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA (2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) Note 1: 2: (1) At this time, the TMRx register is equal to the PRx register. Output signal is shown as active-high. 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 15.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register.
PIC18(L)F2X/45K50 FIGURE 15-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: 15.4.3 T = TOFF – TON All signals are shown as active-high. 2: TON is the turn-on delay of power switch QC and its driver. 3: TOFF is the turn-off delay of power switch QD and its driver.
PIC18(L)F2X/45K50 FIGURE 15-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PxRSEN = 0) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Missing Pulse (ECCPxASE not clear) Timer Overflow Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event ECCPxASE bit Shutdown Event Occurs 15.4.4 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the autoshutdown condition has been removed.
PIC18(L)F2X/45K50 15.4.5 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 15-16: In half-bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC18(L)F2X/45K50 15.4.6 PWM STEERING MODE In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins.
PIC18(L)F2X/45K50 15.4.7 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. The CCPxM<1:0> bits of the CCPxCON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (PxA/PxC and PxB/PxD). The PWM output polarities must be selected before the PWM pin output drivers are enabled.
PIC18(L)F2X/45K50 15.4.8 SETUP FOR ECCP PWM OPERATION USING ECCP1 AND TIMER2 The following steps should be taken when configuring the ECCP1 module for PWM operation using Timer2: 1. 2. 3. 4. 5. 6. 7. 8. Configure the PWM pins to be used (P1A, P1B, P1C, and P1D): • Configure PWM outputs to be used as inputs by setting the corresponding TRIS bits. This prevents spurious outputs during setup. • Set the PSTR1CON bits for each PWM output to be used. Set the PWM period by loading the PR2 register.
PIC18(L)F2X/45K50 TABLE 15-12: REGISTERS ASSOCIATED WITH ENHANCED PWM Name ECCP1AS Bit 7 ECCP1ASE CCP1CON CCPTMRS Bit 6 Bit 5 Bit 4 ECCP1AS<2:0> P1M<1:0> Bit 3 Bit 2 Bit 1 PSS1AC<1:0> DC1B<1:0> Bit 0 PSS1BD<1:0> 210 — C1TSEL 209 CCP1M<3:0> — — — — C2TSEL — Register on page 206 GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 130
PIC18(L)F2X/45K50 15.
PIC18(L)F2X/45K50 REGISTER 15-2: R/x-0 CCPxCON: ENHANCED CCPx CONTROL REGISTER R/W-0 PxM<1:0> R/W-0 R/W-0 DCxB<1:0> R/W-0 R/W-0 R/W-0 R/W-0 CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: (Capture/Compare modes) xx = PxA a
PIC18(L)F2X/45K50 REGISTER 15-2: bit 3-0 CCPxCON: ENHANCED CCPx CONTROL REGISTER (CONTINUED) CCPxM<3:0>: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets the module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = 0101 = 0110 = 0111 = Capture mode: every falling edge Capture mode: every rising edge Capture mode: every 4th rising edge Capture mode: every 16th rising edge 1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set) 1001
PIC18(L)F2X/45K50 REGISTER 15-3: CCPTMRS: PWM TIMER SELECTION CONTROL REGISTER 0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 — — — — C2TSEL — — C1TSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 C2TSEL: CCP2 Timer Selection bit 0 = CCP2 – Capture/Compare modes use TMR1,
PIC18(L)F2X/45K50 REGISTER 15-4: R/W-0 ECCPxAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER R/W-0 ECCPxASE R/W-0 R/W-0 ECCPxAS<2:0> R/W-0 R/W-0 R/W-0 PSSxAC<1:0> R/W-0 PSSxBD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ECCPxASE: CCPx Auto-shutdown Event Status bit if PxRSEN = 1; 1 = An Auto-shutdown event oc
PIC18(L)F2X/45K50 REGISTER 15-5: R/W-0 PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 PxRSEN R/W-0 R/W-0 R/W-0 R/W-0 PxDC<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away;
PIC18(L)F2X/45K50 NOTES: DS30684A-page 212 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 16.0 16.1 The SPI interface supports the following modes and features: MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE • • • • • Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC18(L)F2X/45K50 The I2C interface supports the following modes and features: Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection Figure 16-2 is a block diagram of the I2C interface module in Master mode. Figure 16-3 is a diagram of the I2C interface module in Slave mode.
PIC18(L)F2X/45K50 FIGURE 16-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCL Shift Clock SSPxSR Reg SDA MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Stop bit Detect 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 16.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a chip select known as Slave Select.
PIC18(L)F2X/45K50 FIGURE 16-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SCLK SPI Master SCLK SDO SDI SDI SDO General I/O General I/O SS General I/O SCLK SDI SDO SPI Slave #1 SPI Slave #2 SS SCLK SDI SDO SPI Slave #3 SS 16.2.1 SPI MODE REGISTERS 16.2.2 SPI MODE OPERATION The MSSP module has five registers for SPI mode operation. These are: When initializing the SPI, several options need to be specified.
PIC18(L)F2X/45K50 Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. The MSSP consists of a transmit/receive shift register (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first.
PIC18(L)F2X/45K50 16.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 16-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC18(L)F2X/45K50 16.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPxCON1 register.
PIC18(L)F2X/45K50 FIGURE 16-7: SPI DAISY-CHAIN CONNECTION SCLK SCLK SPI Master SDO SDI SDI SPI Slave #1 SDO General I/O SS SCLK SDI SPI Slave #2 SDO SS SCLK SDI SPI Slave #3 SDO SS FIGURE 16-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPIF Interrupt Flag SSPxSR to SSPxBUF 2012 Microchip Te
PIC18(L)F2X/45K50 FIGURE 16-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 16-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi
PIC18(L)F2X/45K50 16.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/ reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted.
PIC18(L)F2X/45K50 16.3 I2C Mode Overview FIGURE 16-11: The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Figure 16-11 shows the block diagram of the MSSP module when operating in I2C mode.
PIC18(L)F2X/45K50 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching give slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration.
PIC18(L)F2X/45K50 16.4 I2C Mode Operation All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 16.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back.
PIC18(L)F2X/45K50 16.4.5 START CONDITION 16.4.7 RESTART CONDITION The I2C specification defines a Start condition as a transition of SDA from a high-to-low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an active state. Figure 16-10 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid.
PIC18(L)F2X/45K50 I2C Slave Mode Operation 16.4.9 ACKNOWLEDGE SEQUENCE 16.5 The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response.
PIC18(L)F2X/45K50 16.5.2 SLAVE RECEPTION 16.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCL.
DS30684A-page 230 SSPOV BF SSPIF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPxBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent.
2012 Microchip Technology Inc. CKP SSPOV BF SSPIF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSPxBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPxBUF 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent.
DS30684A-page 232 P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPIF is set 4 ACKTIM set by hardware on 8th falling edge of SCL When AHEN=1: CKP is cleared by hardware and SCL is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCL When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL SSPIF i
2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 16.5.3 SLAVE TRANSMISSION 16.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave.
2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 16.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure 16-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
2012 Microchip Technology Inc. D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
PIC18(L)F2X/45K50 16.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 16.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same.
2012 Microchip Technology Inc.
DS30684A-page 240 ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCL If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPxADD is not allowed until 9th falling edge of SCL SSPxBUF can be read anytime before the next received byte Cleared
2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 16.5.6 CLOCK STRETCHING 16.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching.
PIC18(L)F2X/45K50 16.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices.
PIC18(L)F2X/45K50 16.6 I2C Master Mode Master mode is enabled by setting and clearing the appropriate SSPxM bits in the SSPxCON1 register and by setting the SSPxEN bit. In Master mode, the SCL and SDA lines are set as inputs and are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC18(L)F2X/45K50 16.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting.
PIC18(L)F2X/45K50 16.6.4 I2C MASTER MODE START CONDITION TIMING register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. To initiate a Start condition, the user sets the Start Enable bit, SEN, of the SSPxCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count.
PIC18(L)F2X/45K50 16.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPxSTAT register will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out.
PIC18(L)F2X/45K50 16.6.6 I2C MASTER MODE TRANSMISSION 16.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted.
2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 16.6.7 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN, of the SSPxCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/ low-to-high) and data is shifted into the SSPxSR.
2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 16.6.8 ACKNOWLEDGE SEQUENCE TIMING 16.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN, of the SSPxCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC18(L)F2X/45K50 16.6.10 SLEEP OPERATION 2 While in Sleep mode, the I C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 16.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 16.6.
PIC18(L)F2X/45K50 16.6.13 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, then a bus collision has taken place.
PIC18(L)F2X/45K50 16.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 16-32). SCL is sampled low before SDA is asserted low (Figure 16-33). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 16-34).
PIC18(L)F2X/45K50 FIGURE 16-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC18(L)F2X/45K50 16.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 16-35). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC18(L)F2X/45K50 16.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 16-37).
PIC18(L)F2X/45K50 TABLE 16-3: Name ANSELB INTCON REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 155 TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120 RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129 GIE/GIEH PEIE/GIEL ADIP IPR1 ACTIP IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 130 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 126 PIE2 OSCFIE C1IE C2
PIC18(L)F2X/45K50 16.7 Baud Rate Generator The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 16-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line.
PIC18(L)F2X/45K50 16.
PIC18(L)F2X/45K50 REGISTER 16-2: SSPxCON1: SSPx CONTROL REGISTER 1 R/C/HS-0 R/C/HS-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP R/W-0 R/W-0 R/W-0 R/W-0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to
PIC18(L)F2X/45K50 REGISTER 16-2: bit 3-0 SSPxCON1: SSPx CONTROL REGISTER 1 (CONTINUED) SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slav
PIC18(L)F2X/45K50 REGISTER 16-3: SSPxCON2: SSPx CONTROL REGISTER 2 R/W-0 R-0 R/W-0 R/S/HC-0 R/S/HC-0 R/S/HC-0 R/S/HC-0 R/W/HC-0 GCEN ACKSTAT ACKDT ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit
PIC18(L)F2X/45K50 REGISTER 16-4: SSPxCON3: SSPx CONTROL REGISTER 3 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowled
PIC18(L)F2X/45K50 REGISTER 16-4: SSPxCON3: SSPx CONTROL REGISTER 3 (CONTINUED) DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSPxCON1 register and SCL is held low. 0 = Data holding is disabled bit 0 Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte.
PIC18(L)F2X/45K50 SSPxADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) REGISTER 16-6: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mod
PIC18(L)F2X/45K50 NOTES: DS30684A-page 268 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 17.0 The EUSART module includes the following capabilities: ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) • • • • • • • • • • The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution.
PIC18(L)F2X/45K50 FIGURE 17-2: EUSART RECEIVE BLOCK DIAGRAM CREN RX/DT pin Baud Rate Generator Data Recovery FOSC BRG16 SPBRGHx SPBRGx Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREGx Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTAx) •
PIC18(L)F2X/45K50 17.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC18(L)F2X/45K50 17.1.1.5 TSR Status 17.1.1.7 The TRMT bit of the TXSTAx register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREGx. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status. 1. 2. 3. 4.
PIC18(L)F2X/45K50 FIGURE 17-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx Word 2 Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 Word 1 1 TCY TXIF bit (Interrupt Reg. Flag) bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg Word 2 Transmit Shift Reg This timing diagram shows two consecutive transmissions.
PIC18(L)F2X/45K50 17.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 17-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC18(L)F2X/45K50 17.1.2.4 Receive Interrupts The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software.
PIC18(L)F2X/45K50 17.1.2.9 Asynchronous Reception Setup: 1. Initialize the SPBRGHx:SPBRGx register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 17.4 “EUSART Baud Rate Generator (BRG)”). 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. 3. Enable the serial port by setting the SPEN bit and the RX/DT pin TRIS bit. The SYNC bit must be clear for asynchronous operation. 4.
PIC18(L)F2X/45K50 FIGURE 17-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin bit 1 Start bit bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg bit 0 Start bit bit 7/8 Stop bit Word 2 RCREGx Word 1 RCREGx RCIDL bit 7/8 Stop bit Read Rcv Buffer Reg RCREGx RCIF (Interrupt Flag) OERR bit CREN This timing diagram shows three words appearing on the RX/DT input. The RCREGx (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
PIC18(L)F2X/45K50 17.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output.
PIC18(L)F2X/45K50 17.
PIC18(L)F2X/45K50 REGISTER 17-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6
PIC18(L)F2X/45K50 REGISTER 17-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bi
PIC18(L)F2X/45K50 17.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCONx register selects 16-bit mode. The SPBRGHx:SPBRGx register pair determines the period of the free running baud rate timer.
PIC18(L)F2X/45K50 TABLE 17-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 281 — UARTMD USBMD ACTMD — SPEN RX9 SREN CREN ADDEN PMD0 RCSTA1 SPBRG1 EUSART Baud Rate Generator, Low Byte SPBRGH1 EUSART Baud Rate Generator, High Byte PIR1 TXSTA1 Legend: TMR3MD TMR2MD TMR1MD FERR OERR 64 RX9D 280 — — ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR
PIC18(L)F2X/45K50 TABLE 17-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 48.000 MHz Actual Rate % Error SPBRGx value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRGx value (decimal) FOSC = 16.000 MHz Actual Rate % Error FOSC = 11.
PIC18(L)F2X/45K50 TABLE 17-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz FOSC = 4.000 MHz Actual Rate % Error SPBRGHx: SPBRGx (decimal) Actual Rate % Error FOSC = 3.6864 MHz SPBRGHx: SPBRGx (decimal) Actual Rate % Error FOSC = 1.000 MHz SPBRGHx :SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) 207 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 1200 1199 -0.08 416 1202 0.
PIC18(L)F2X/45K50 17.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. and SPBRGx registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 17.4.3 “Auto-Wake-up on Break”).
PIC18(L)F2X/45K50 17.4.2 AUTO-BAUD OVERFLOW 17.4.3.1 Special Considerations During the course of automatic baud detection, the ABDOVF bit of the BAUDCONx register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGHx:SPBRGx register pair.
PIC18(L)F2X/45K50 FIGURE 17-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREGx The EUSART remains in Idle while the WUE bit is set.
PIC18(L)F2X/45K50 17.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTAx register. The Break character transmission is then initiated by a write to the TXREGx. The value of data written to TXREGx will be ignored and all ‘0’s will be transmitted.
PIC18(L)F2X/45K50 17.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC18(L)F2X/45K50 17.5.1.5 1. 2. 3. Synchronous Master Transmission Setup: 4. Initialize the SPBRGHx, SPBRGx register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 17.4 “EUSART Baud Rate Generator (BRG)”). Set the RX/DT and TX/CK TRIS controls to ‘1’. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Set the TRIS bits corresponding to the RX/DT and TX/ CK I/O pins. 5. 6. 7. FIGURE 17-10: 8. 9.
PIC18(L)F2X/45K50 TABLE 17-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 281 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 126 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
PIC18(L)F2X/45K50 17.5.1.6 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver must be disabled by setting the corresponding TRIS bits when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTAx register) or the Continuous Receive Enable bit (CREN of the RCSTAx register).
PIC18(L)F2X/45K50 FIGURE 17-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREGx Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC18(L)F2X/45K50 17.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXSTAx register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTAx register configures the device as a slave.
PIC18(L)F2X/45K50 TABLE 17-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 281 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 129 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 126 PIR1 ACTIF ADIF RCIF TXIF SSP1F CCP1IF TMR2IF TMR1IF 1
PIC18(L)F2X/45K50 17.5.2.3 EUSART Synchronous Slave Reception 17.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 17.5.1.6 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC18(L)F2X/45K50 NOTES: DS30684A-page 298 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 18.0 The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC18(L)F2X/45K50 18.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 18.1.1 PORT CONFIGURATION The ANSELx and TRISx registers configure the A/D port pins.
PIC18(L)F2X/45K50 18.1.5 CONVERSION CLOCK 18.1.6 The source of the conversion clock is software selectable via the ADCS bits of the ADCON2 register. There are seven possible clock options: • • • • • • • The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital Conversion. The ADC interrupt enable is the ADIE bit in the PIE1 register and the interrupt priority is the ADIP bit in the IPR1 register. The ADC interrupt flag is the ADIF bit in the PIR1 register.
PIC18(L)F2X/45K50 18.1.7 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON2 register controls the output format. Figure 18-2 shows the two output formats.
PIC18(L)F2X/45K50 18.2 Figure 18-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into SLEEP mode before the conversion begins. ADC Operation 18.2.1 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’.
PIC18(L)F2X/45K50 18.2.2 COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF flag bit • Update the ADRESH:ADRESL registers with new conversion result 18.2.3 DISCHARGE The discharge phase is used to initialize the value of the capacitor array. The array is discharged after every sample.
PIC18(L)F2X/45K50 18.2.10 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC18(L)F2X/45K50 18.
PIC18(L)F2X/45K50 REGISTER 18-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 TRIGSEL — — — R/W-0 R/W-0 R/W-0 PVCFG<1:0> R/W-0 NVCFG<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TRIGSEL: Special Trigger Select bit 1 = Selects the special trigger from CTMU 0 = Selects the special trigger from CCP2 bit 6-4 Unimplemented: Read as ‘0’ bit 3-2 PVCFG<1:0>: Positive Voltag
PIC18(L)F2X/45K50 REGISTER 18-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 ADFM — R/W-0 R/W-0 R/W-0 R/W-0 ACQT<2:0> R/W-0 R/W-0 ADCS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 x = Bit is unknown ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition time select bits.
PIC18(L)F2X/45K50 REGISTER 18-4: R/W-x ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 18-5: R/W-x ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x R/W-x R/W-x R/W
PIC18(L)F2X/45K50 18.4 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 18-5. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 18-5.
PIC18(L)F2X/45K50 FIGURE 18-5: ANALOG INPUT MODEL VDD Rs VA ANx RIC 1k CPIN 5 pF I LEAKAGE(1) Sampling Switch SS Rss CHOLD = 13.5 pF Legend: CPIN = Input Capacitance I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC SS = Sampling Switch CHOLD = Sample/Hold Capacitance Note 1: VDD Discharge Switch VSS/VREF- 3.5V 3.0V 2.5V 2.0V 1.5V .1 1 10 Rss (k) 100 See Section 29.0 “Electrical Characteristics”.
PIC18(L)F2X/45K50 TABLE 18-2: Name REGISTERS ASSOCIATED WITH A/D OPERATION Bit 7 Bit 6 Bit 5 — ADCON0 — ADCON1 TRIGSEL — ADFM — ADCON2 A/D Result, High Byte ADRESL A/D Result, Low Byte — Bit 3 Bit 2 CHS<4:0> ADRESH ANSELA Bit 4 — PVCFG<1:0> ACQT<2:0> Bit 1 Bit 0 GO/DONE ADON NVCFG<1:0> ADCS<2:0> Register on page 306 307 308 309 309 — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 154 155 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 ANSELC ANSC7 ANSC6 — — — ANSC2 — —
PIC18(L)F2X/45K50 19.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution.
PIC18(L)F2X/45K50 FIGURE 19-2: COMPARATOR C1/C2 SIMPLIFIED BLOCK DIAGRAM CxCH<1:0> 2 C12IN0- 0 C12IN1- 1 C12IN2- CxON(1) CxSP D CxVIN- 2 C12IN3- CxVIN+ 3 Q1 - (2),(3) EN Cx + D Q3(2) DAC Output Read or Write of CMxCON0 0 FVR BUF1 1 To Interrupts (CxIF) Reset 0 1 Q EN CL CxR CxIN+ Q To CMxCON0 (CxOUT) CM2CON1 (MCxOUT) async_CXOUT CxPOL CxSYNC CXVREF to PWM Logic CxOE TRIS bit 0 CXRSEL D Q 1 CxOUT Timer1 Clock sync_CxOUT - to SR Latch - to TxG MUX(4) Note 1: 2: 3: 4: W
PIC18(L)F2X/45K50 19.2 Comparator Control Each comparator has a separate control and Configuration register: CM1CON0 for Comparator C1 and CM2CON0 for Comparator C2. In addition, Comparator C2 has a second control register, CM2CON1, for controlling the interaction with Timer1 and simultaneous reading of both comparator outputs.
PIC18(L)F2X/45K50 19.4 Comparator Interrupt Operation The comparator interrupt flag will be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figure 19-2). The first latch is updated with the comparator output value, when the CMxCON0 register is read or written. The value is latched on the third cycle of the system clock, also known as Q3.
PIC18(L)F2X/45K50 19.5 Operation During Sleep 19.7 The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in Section 29.0 “Electrical Characteristics”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register.
PIC18(L)F2X/45K50 19.8 Additional Comparator Features There are four additional comparator features: • • • • Simultaneous read of comparator outputs Internal reference selection Hysteresis selection Output Synchronization 19.8.1 SIMULTANEOUS COMPARATOR OUTPUT READ The MC1OUT and MC2OUT bits of the CM2CON1 register are mirror copies of both comparator outputs. The ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers.
PIC18(L)F2X/45K50 19.
PIC18(L)F2X/45K50 REGISTER 19-2: CM2CON1: COMPARATOR 1 AND 2 CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 MC1OUT MC2OUT C1RSEL C2RSEL — — C1SYNC C2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5 C1RSEL: Comparator C1 Reference Select bit 1 = FVR BUF1 routed to C1VREF input 0 = DAC r
PIC18(L)F2X/45K50 TABLE 19-2: Name ANSELA ANSELB REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 154 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 155 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 320 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH<1:0> 319 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH<1:0> 319 — VREFCON1 DACEN DACLPS DACOE VREFCON
PIC18(L)F2X/45K50 NOTES: DS30684A-page 322 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 20.0 CHARGE TIME MEASUREMENT UNIT (CTMU) The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. By working with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses with a specific time delay.
PIC18(L)F2X/45K50 20.1 CTMU Operation The CTMU works by using a fixed current source to charge a circuit. The type of circuit depends on the type of measurement being made. In the case of charge measurement, the current is fixed and the amount of time the current is applied to the circuit is fixed. The amount of voltage read by the A/D is then a measurement of the capacitance of the circuit. In the case of time measurement, the current, as well as the capacitance of the circuit, is fixed.
PIC18(L)F2X/45K50 20.1.4 EDGE STATUS The CTMUCONL register also contains two status bits: EDG2STAT and EDG1STAT (CTMUCONL<1:0>). Their primary function is to show if an edge response has occurred on the corresponding channel. The CTMU automatically sets a particular bit when an edge response is detected on its channel.
PIC18(L)F2X/45K50 20.3 Calibrating the CTMU Module FIGURE 20-2: The CTMU requires calibration for precise measurements of capacitance and time, as well as for accurate time delay. If the application only requires measurement of a relative change in capacitance or time, calibration is usually not necessary.
PIC18(L)F2X/45K50 EXAMPLE 20-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.
PIC18(L)F2X/45K50 EXAMPLE 20-2: CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 #define DELAY for(i=0;i
PIC18(L)F2X/45K50 20.3.2 CAPACITANCE CALIBRATION There is a small amount of capacitance from the internal A/D Converter sample capacitor as well as stray capacitance from the circuit board traces and pads that affect the precision of capacitance measurements. A measurement of the stray capacitance can be taken by making sure the desired capacitance to be measured has been removed. The measurement is then performed using the following steps: 1. 2. 3. 4. 5. 6. Initialize the A/D Converter and the CTMU.
PIC18(L)F2X/45K50 EXAMPLE 20-3: CAPACITANCE CALIBRATION ROUTINE #include "p18cxxx.h" #define #define #define #define bits #define #define COUNT 25 ETIME COUNT*2.5 DELAY for(i=0;i
PIC18(L)F2X/45K50 20.4 Measuring Capacitance with the CTMU There are two separate methods of measuring capacitance with the CTMU. The first is the absolute method, in which the actual capacitance value is desired. The second is the relative method, in which the actual capacitance is not needed, rather an indication of a change in capacitance is required. 20.4.1 ABSOLUTE CAPACITANCE MEASUREMENT For absolute capacitance measurements, both the current and capacitance calibration steps found in Section 20.
PIC18(L)F2X/45K50 EXAMPLE 20-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH #include "p18cxxx.h" #define #define #define #define COUNT 500 DELAY for(i=0;i
PIC18(L)F2X/45K50 20.5 It is assumed that the time measured is small enough that the capacitance, COFFSET, provides a valid voltage to the A/D Converter. For the smallest time measurement, always set the A/D Channel Select register (AD1CHS) to an unused A/D channel; the corresponding pin for which is not connected to any circuit board trace. This minimizes added stray capacitance, keeping the total circuit capacitance close to that of the A/D Converter itself (4-5 pF).
PIC18(L)F2X/45K50 20.6 An example use of this feature is for interfacing with variable capacitive-based sensors, such as a humidity sensor. As the humidity varies, the pulse width output on CTPLS will vary. The CTPLS output pin can be connected to an input capture pin and the varying pulse width is measured to determine the humidity in the application.
PIC18(L)F2X/45K50 20.9 Effects of a Reset on CTMU 20.10 Registers Upon Reset, all registers of the CTMU are cleared. This leaves the CTMU module disabled, its current source is turned off and all configuration options return to their default settings. The module needs to be re-initialized following any Reset. There are three control registers for the CTMU: If the CTMU is in the process of taking a measurement at the time of Reset, the measurement will be lost.
PIC18(L)F2X/45K50 REGISTER 20-2: R/W-0 CTMUCONL: CTMU CONTROL REGISTER 1 R/W-0 EDG2POL R/W-0 EDG2SEL<1:0> R/W-0 EDG1POL R/W-0 R/W-0 EDG1SEL<1:0> R/W-0 R/W-0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response bit 6-5 EDG2SEL<1:0>: E
PIC18(L)F2X/45K50 REGISTER 20-3: R/W-0 CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM<5:0> R/W-0 IRNG<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . .
PIC18(L)F2X/45K50 NOTES: DS30684A-page 338 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 21.0 SR LATCH The module consists of a single SR latch with multiple Set and Reset inputs as well as separate latch outputs. The SR latch module includes the following features: • • • • Programmable input selection SR latch output is available internally/externally Selectable Q and Q output Firmware Set and Reset The SR latch can be used in a variety of analog applications, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing applications. 21.
PIC18(L)F2X/45K50 FIGURE 21-1: DIVSRCLK BLOCK DIAGRAM 3 SRCLK<2:0> Programmable SRCLK divider 1:4 to 1:512 Peripheral Clock t0 t0+4 t0+8 DIVSRCLK 4-512 cycles ...
PIC18(L)F2X/45K50 TABLE 21-1: DIVSRCLK FREQUENCY TABLE SRCLK<2:0> Divider FOSC = 20 MHz FOSC = 16 MHz 111 512 25.6 s 32 s 64 s 128 s 512 s 110 256 12.8 s 16 s 32 s 64 s 256 s 101 128 6.4 s 8 s 16 s 32 s 128 s 100 64 3.2 s 4 s 8 s 16 s 64 s 011 32 1.6 s 2 s 4 s 8 s 32 s 010 16 0.8 s 1 s 2 s 4 s 16 s 001 8 0.4 s 0.5 s 1 s 2 s 8 s 000 4 0.2 s 0.25 s 0.5 s 1 s 4 s 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 21.
PIC18(L)F2X/45K50 REGISTER 21-2: SRCON1: SR LATCH CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SRI pin status sets SR latch 0 = SRI pin status has no effect on SR latch bit 6 SRSCKE:
PIC18(L)F2X/45K50 NOTES: DS30684A-page 344 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 22.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: • • • • ADC input channel ADC positive reference Comparator positive input Digital-to-Analog Converter (DAC) The FVR can be enabled by setting the FVREN bit of the VREFCON0 register. 22.
PIC18(L)F2X/45K50 22.
PIC18(L)F2X/45K50 23.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The negative voltage source is disabled by setting the DACLPS bit in the VREFCON1 register. Clearing the DACLPS bit in the VREFCON1 register disables the positive voltage source. 23.
PIC18(L)F2X/45K50 FIGURE 23-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) Reserved 11 10 FVR BUF1 VREF+ VSRC+ 01 00 VDD DACR<4:0> 5 R 2 R DACPSS<1:0> R DACEN DACLPS 11111 11110 R 32 Steps R 32-to-1 MUX R R R 00001 DACOUT 00000 DACOE DACNSS FIGURE 23-2: VREF- 1 VSS 0 DAC Output (to Comparators and ADC Modules) VSRC- VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS30684A-page 348 DACOUT + –
PIC18(L)F2X/45K50 23.7 Operation During Sleep 23.8 When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the VREFCON1 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 23.
PIC18(L)F2X/45K50 REGISTER 23-2: VREFCON2: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACR<4:0>: DAC Voltage Output Select bits VOUT = ((VSRC+) - (VSRC-))*(DACR<4:0>/(25
PIC18(L)F2X/45K50 UNIVERSAL SERIAL BUS (USB) host and the PIC® microcontroller. The SIE can be interfaced directly to the USB by utilizing the internal transceiver. This section describes the details of the USB peripheral. Because of the very specific nature of the module, knowledge of USB is expected. Some high-level USB information is provided in Section 3.14 “Oscillator Settings for USB” only for application design reference.
PIC18(L)F2X/45K50 24.2 USB Status and Control The operation of the USB module is configured and managed through three control registers. In addition, a total of 14 registers are used to manage the actual USB transactions. The registers are: • • • • • • USB Control register (UCON) USB Configuration register (UCFG) USB Transfer Status register (USTAT) USB Device Address register (UADDR) Frame Number registers (UFRMH:UFRML) Endpoint Enable registers 0 through 7 (UEPn) 24.2.
PIC18(L)F2X/45K50 REGISTER 24-1: UCON: USB CONTROL REGISTER U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0 — PPBRST SE0 PKTDIS USBEN(1) RESUME SUSPND — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) b
PIC18(L)F2X/45K50 The PPBRST bit (UCON<6>) controls the Reset status when Double-Buffering mode (ping-pong buffering) is used. When the PPBRST bit is set, all Ping-Pong Buffer Pointers are set to the Even buffers. PPBRST has to be cleared by firmware. This bit is ignored in buffering modes not using ping-pong buffering. The PKTDIS bit (UCON<4>) is a flag indicating that the SIE has disabled packet transmission and reception.
PIC18(L)F2X/45K50 REGISTER 24-2: UCFG: USB CONFIGURATION REGISTER (BANKED F39h) R/W-0 R/W-0 U-0 UTEYE UOEMON — R/W-0 R/W-0 UPUEN(1,2) UTRDIS(1,3) R/W-0 R/W-0 FSEN(1) R/W-0 PPB<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test is enabled 0 = Eye pattern test is disabled bit 6 UOEMON: USB OE Monitor
PIC18(L)F2X/45K50 24.2.2.2 Internal Pull-up Resistors The PIC18F2X/45K50 devices have built-in pull-up resistors designed to meet the requirements for low-speed and full-speed USB. The UPUEN bit (UCFG<4>) enables the internal pull-ups. Figure 24-1 shows the pull-ups and their control. Note: 24.2.2.3 The official USB specifications require that USB devices must never source any current onto the +5V VBUS line of the USB cable.
PIC18(L)F2X/45K50 24.2.3 USB STATUS REGISTER (USTAT) The USB Status register reports the transaction status within the SIE. When the SIE issues a USB transfer complete interrupt, USTAT should be read to determine the status of the transfer. USTAT contains the transfer endpoint number, direction and Ping-Pong Buffer Pointer value (if used). Note: Clearing the transfer complete flag bit, TRNIF, causes the SIE to advance the FIFO.
PIC18(L)F2X/45K50 24.2.4 USB ENDPOINT CONTROL Each of the 16 possible bidirectional endpoints has its own independent control register, UEPn (where ‘n’ represents the endpoint number). Each register has an identical complement of control bits. The prototype is shown in Register 24-4. The EPHSHK bit (UEPn<4>) controls handshaking for the endpoint; setting this bit enables USB handshaking. Typically, this bit is always set except when using isochronous endpoints.
PIC18(L)F2X/45K50 24.2.5 USB ADDRESS REGISTER (UADDR) FIGURE 24-4: The USB Address register contains the unique USB address that the peripheral will decode when active. UADDR is reset to 00h when a USB Reset is received, indicated by URSTIF, or when a Reset is received from the microcontroller. The USB address must be written by the microcontroller during the USB setup phase (enumeration) as part of the Microchip USB firmware support. 24.2.
PIC18(L)F2X/45K50 24.4 Buffer Descriptors and the Buffer Descriptor Table The registers in Bank 4 are used specifically for endpoint buffer control in a structure known as the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configuration. The BDT is composed of Buffer Descriptors (BD) which are used to define and control the actual buffers in the USB RAM space.
PIC18(L)F2X/45K50 The BDnSTAT byte of the BDT should always be the last byte updated when preparing to arm an endpoint. The SIE will clear the UOWN bit when a transaction has completed. No hardware mechanism exists to block access when the UOWN bit is set. Thus, unexpected behavior can occur if the microcontroller attempts to modify memory when the SIE owns it. Similarly, reading such memory may produce inaccurate data until the USB peripheral returns ownership to the microcontroller. 24.4.1.
PIC18(L)F2X/45K50 REGISTER 24-5: R/W-x UOWN(1) BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), CPU MODE (BANKED 4xxh) R/W-x U-0 U-0 (2) (3) (3) DTS — — R/W-x R/W-x R/W-x R/W-x DTSEN BSTALL BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit(1) 0 = The microcontroller core owns the BD and its corresponding buffer
PIC18(L)F2X/45K50 24.4.1.3 BDnSTAT Register (SIE Mode) When the BD and its buffer are owned by the SIE, most of the bits in BDnSTAT take on a different meaning. The configuration is shown in Register 24-6. Once the UOWN bit is set, any data or control settings previously written there by the user will be overwritten with data from the SIE. The BDnSTAT register is updated by the SIE with the token Packet Identifier (PID) which is stored in BDnSTAT<5:3>.
PIC18(L)F2X/45K50 24.4.4 PING-PONG BUFFERING the completion of a transaction (UOWN cleared by the SIE), the pointer is toggled to the Odd BD. After the completion of the next transaction, the pointer is toggled back to the Even BD and so on. An endpoint is defined to have a ping-pong buffer when it has two sets of BD entries: one set for an Even transfer and one set for an Odd transfer. This allows the CPU to process one BD while the SIE is processing the other BD.
PIC18(L)F2X/45K50 TABLE 24-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES BDs Assigned to Endpoint Mode 0 (No Ping-Pong) Endpoint Mode 1 (Ping-Pong on EP0 OUT) Mode 2 (Ping-Pong on all EPs) Mode 3 (Ping-Pong on all other EPs, except EP0) Out In Out In Out In Out In 0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1 1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O) 2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O) 3 6
PIC18(L)F2X/45K50 24.5 Figure 24-7 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB Status interrupts; these are enabled and flagged in the UIE and UIR registers, respectively. The second level consists of USB error conditions, which are enabled and flagged in the UEIR and UEIE registers. An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the top level.
PIC18(L)F2X/45K50 24.5.1 USB INTERRUPT STATUS REGISTER (UIR) When the USB module is in the Low-Power Suspend mode (UCON<1> = 1), the SIE does not get clocked. When in this state, the SIE cannot process packets and, therefore, cannot detect new interrupt conditions other than the Activity Detect Interrupt, ACTVIF. The ACTVIF bit is typically used by USB firmware to detect when the microcontroller should bring the USB module out of the Low-Power Suspend mode (UCON<1> = 0).
PIC18(L)F2X/45K50 24.5.1.1 Bus Activity Detect Interrupt Bit (ACTVIF) The ACTVIF bit cannot be cleared immediately after the USB module wakes up from Suspend or while the USB module is suspended. A few clock cycles are required to synchronize the internal hardware state machine before the ACTVIF bit can be cleared by firmware. Clearing the ACTVIF bit before the internal hardware is synchronized may not have an effect on the value of ACTVIF.
PIC18(L)F2X/45K50 24.5.2 USB INTERRUPT ENABLE REGISTER (UIE) The USB Interrupt Enable register (Register 24-8) contains the enable bits for the USB Status interrupt sources. Setting any of these bits will enable the respective interrupt source in the UIR register. REGISTER 24-8: The values in this register only affect the propagation of an interrupt condition to the microcontroller’s interrupt logic.
PIC18(L)F2X/45K50 24.5.3 USB ERROR INTERRUPT STATUS REGISTER (UEIR) The USB Error Interrupt Status register (Register 24-9) contains the flag bits for each of the error sources within the USB peripheral. Each of these sources is controlled by a corresponding interrupt enable bit in the UEIE register. All of the USB error flags are ORed together to generate the USB Error Interrupt Flag (UERRIF) at the top level of the interrupt logic.
PIC18(L)F2X/45K50 24.5.4 USB ERROR INTERRUPT ENABLE REGISTER (UEIE) As with the UIE register, the enable bits only affect the propagation of an interrupt condition to the microcontroller’s interrupt logic. The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt. The USB Error Interrupt Enable register (Register 24-10) contains the enable bits for each of the USB error interrupt sources.
PIC18(L)F2X/45K50 24.6 24.6.2 USB Power Modes Many USB applications will likely have several different sets of power requirements and configuration. The most common power modes encountered are Bus Power Only, Self-Power Only and Dual Power with Self-Power Dominance. The most common cases are presented here. Also provided is a means of estimating the current consumption of the USB transceiver. 24.6.
PIC18(L)F2X/45K50 24.6.3 DUAL POWER WITH SELF-POWER DOMINANCE 24.6.4 USB TRANSCEIVER CURRENT CONSUMPTION Some applications may require a dual power option. This allows the application to use internal power primarily, but switch to power from the USB when no internal power is available. Figure 24-11 shows a simple Dual Power with Self-Power Dominance mode example, which automatically switches between Self-Power Only and USB Bus Power Only modes.
PIC18(L)F2X/45K50 EQUATION 24-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION IXCVR = Legend: (60 mA • VUSB3V3 • PZERO • PIN • LCABLE) + IPULLUP (3.3V • 5m) VUSB: Voltage applied to the VUSB3V3 pin in volts. (Should be 3.0V to 3.6V.) PZERO: Percentage (in decimal) of the IN traffic bits sent by the PIC® device that are a value of ‘0’. PIN: Percentage (in decimal) of total bus bandwidth that is used for IN traffic. LCABLE: Length (in meters) of the USB cable. The USB 2.
PIC18(L)F2X/45K50 24.7 Oscillator The USB module has specific clock requirements. For full-speed operation, the clock source must be 48 MHz. Even so, the microcontroller core and other peripherals are not required to run at that clock speed. Available clocking options are described in detail in Section 3.14 “Oscillator Settings for USB”. 24.8 Interrupt-On-Change for D+/Dpins The PIC18(L)F2X/45K50 has interrupt-on-change functionality on both D+ and D- data pins.
PIC18(L)F2X/45K50 TABLE 24-4: Name INTCON REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 120 IPR3 — — — — CTMUIP USBIP TMR3GIP TMR1GIP 131 PIR3 — — — — CTMUIF USBIF TMR3GIF TMR1GIF 125 PIE3 — — — — CTMUIE USBIE TMR3GIE TMR1GIE 128 UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 353 UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN
PIC18(L)F2X/45K50 24.10 Overview of USB 24.10.3 This section presents some of the basic USB concepts and useful information necessary to design a USB device. Although much information is provided in this section, there is a plethora of information provided within the USB specifications and class specifications. Thus, the reader is encouraged to refer to the USB specifications for more information (www.usb.org).
PIC18(L)F2X/45K50 The USB specification limits the power taken from the bus. Each device is ensured 100 mA at approximately 5V (one unit load). Additional power may be requested, up to a maximum of 500 mA. Note that power above one unit load is a request and the host or hub is not obligated to provide the extra current. Thus, a device capable of consuming more than one unit load must be able to maintain a low-power configuration of a one unit load or less, if necessary.
PIC18(L)F2X/45K50 25.0 HIGH/LOW-VOLTAGE DETECT (HLVD) The PIC18(L)F2X/45K50 devices have a High/LowVoltage Detect module (HLVD). This is a programmable circuit that sets both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution branches to the interrupt vector address and the software responds to the interrupt. 25.
PIC18(L)F2X/45K50 The module is enabled by setting the HLVDEN bit (HLVDCON<4>). Each time the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit (HLVDCON<5>) is a read-only bit used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. trip point voltage.
PIC18(L)F2X/45K50 25.3 HLVD Setup 25.4 To set up the HLVD module: 1. 2. 3. 4. 5. When the module is enabled, the HLVD comparator and voltage divider are enabled and consume static current. The total current consumption, when enabled, is specified in Section 29.0 “Electrical Characteristics”. Depending on the application, the HLVD module does not need to operate constantly. To reduce current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked.
PIC18(L)F2X/45K50 FIGURE 25-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VHLVD VDD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VHLVD VDD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists Applications In many applications, it is desirable to detect a drop below, or rise above, a particular voltage t
PIC18(L)F2X/45K50 25.7 Operation During Sleep 25.8 When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 25-1: Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off.
PIC18(L)F2X/45K50 NOTES: DS30684A-page 384 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 26.0 SPECIAL FEATURES OF THE CPU PIC18(L)F2X/45K50 devices include several features intended to maximize reliability and minimize cost through elimination of external components.
PIC18(L)F2X/45K50 TABLE 26-1: Address CONFIGURATION BITS AND DEVICE IDs Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 300000h CONFIG1L — — LS48MHZ CPUDIV<1:0> 300001h CONFIG1H IESO FCMEN PCLKEN — 300002h CONFIG2L — LPBOR — 300003h CONFIG2H — — 300004h CONFIG3L — — 300005h CONFIG3H MCLRE 300006h CONFIG4L DEBUG 300007h CONFIG4H — Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value — CFGPLLEN PLLSEL 0000 0000 FOSC<3:0> BORV<1:0> 0010 0101 BOREN<1:0> WDTPS<3:0> PWRTEN 0101
PIC18(L)F2X/45K50 26.
PIC18(L)F2X/45K50 REGISTER 26-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH R/P-0 R/P-0 R/P-1 U-0 IESO FCMEN PCLKEN — R/P-0 R/P-1 R/P-0 R/P-1 FOSC<3:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7 IESO(1): Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN(1): Fail-Safe Clock Monitor Enable bit
PIC18(L)F2X/45K50 REGISTER 26-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW U-0 R/P-1 U-0 — LPBOR — R/P-1 R/P-1 BORV<1:0>(1) R/P-1 R/P-1 BOREN<1:0>(2) R/P-1 PWRTEN(2) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 LPBOR: Low-Power Brown-out Reset Enable bits 1 = Low-Power Brown-out Reset disabled 0 = Low-Power Brown-out Reset enabled bit 5 Unimp
PIC18(L)F2X/45K50 REGISTER 26-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH U-0 U-0 — — R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 WDTPS<3:0> R/P-1 WDTEN<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:51
PIC18(L)F2X/45K50 REGISTER 26-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH R/P-1 R/P-1 U-0 R/P-1 U-0 U-0 R/P-1 R/P-1 MCLRE SDOMX — T3CMX — — PBADEN CCP2MX bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6 SDOMX: SDO Output MUX bit 1 = SDO is on RB3 0 = SDO is o
PIC18(L)F2X/45K50 REGISTER 26-6: R/P-1 DEBUG CONFIG4L: CONFIGURATION REGISTER 4 LOW R/P-0 (2) XINST R/P-1 ICPRT U-0 (3) — U-0 — R/P-1 LVP (1) U-0 R/P-1 — STVREN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit(2) 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 a
PIC18(L)F2X/45K50 REGISTER 26-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1) CP2(1) CP1 CP0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 not code-protected 0 = Block 3 code-protected bit 2 CP2: Code Protection bit(1) 1 = Block 2 not code-protected 0 = Block 2 cod
PIC18(L)F2X/45K50 REGISTER 26-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3(1) WRT2(1) WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 not write-protected 0 = Block 3 write-protected bit 2 WRT2: Write Protection bit(1) 1 = Block 2 not write-protected 0 =
PIC18(L)F2X/45K50 REGISTER 26-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH R/C-1 R/C-1 WRTD WRTB R/C-1 (1) WRTC U-0 U-0 U-0 U-0 U-0 — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot Block not write-protected 0 = Boot Block write
PIC18(L)F2X/45K50 REGISTER 26-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot Block not protected from table reads executed in other blocks 0 = Boot Block protected from table reads executed in other blocks bit
PIC18(L)F2X/45K50 TABLE 26-2: DEVICE ID TABLE FOR THE PIC18(L)F2X/45K50 FAMILY DEV<10:3> 0101 1100 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 26.3 Watchdog Timer (WDT) For PIC18(L)F2X/45K50 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes).
PIC18(L)F2X/45K50 26.3.1 CONTROL REGISTER Register 26-15 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable Configuration bit, but only if the Configuration bit has disabled the WDT. 26.
PIC18(L)F2X/45K50 26.5 Each of the blocks has three code protection bits associated with them. They are: Program Verification and Code Protection • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC® microcontroller devices.
PIC18(L)F2X/45K50 26.5.1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to or written from any location using the table read and table write instructions. The device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. instruction that executes from a location outside of that block is not allowed to read and will result in reading ‘0’s.
PIC18(L)F2X/45K50 FIGURE 26-4: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 0008FFh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 001FFFh 002000h PC = 003FFEh WRT1, EBTR1 = 11 TBLRD* 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’.
PIC18(L)F2X/45K50 26.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings. 26.5.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected.
PIC18(L)F2X/45K50 26.10 Single-Supply ICSP Programming The LVP Configuration bit enables Single-Supply ICSP Programming (formerly known as Low-Voltage ICSP Programming or LVP). When Single-Supply Programming is enabled, the microcontroller can be programmed without requiring high voltage being applied to the MCLR/VPP/RE3 pin. See “PIC18(L)F2X/4XK50 Flash Memory Programming Specification” (DS41630) for more details about low voltage programming.
PIC18(L)F2X/45K50 27.0 INSTRUCTION SET SUMMARY PIC18(L)F2X/45K50 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of eight new instructions, for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 27.
PIC18(L)F2X/45K50 TABLE 27-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18(L)F2X/45K50 FIGURE 27-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111
PIC18(L)F2X/45K50 TABLE 27-2: PIC18 INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f
PIC18(L)F2X/45K50 TABLE 27-2: PIC18 INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1 (2) 1 (2) 1
PIC18(L)F2X/45K50 TABLE 27-2: PIC18 INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from
PIC18(L)F2X/45K50 27.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18(L)F2X/45K50 ADDWFC ADD W and CARRY bit to f ANDLW Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z f {,d {,a}} Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da Encoding: ffff ffff Add W, the CARRY flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F2X/45K50 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] Operands: -128 n 127 Operation: if CARRY bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 Description: Encoding: 01da ffff ffff The contents of W are AND’ed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18(L)F2X/45K50 BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] Operands: -128 n 127 Operation: if NEGATIVE bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None f, b {,a} Operation: 0 f Status Affected: None Encoding: Encoding: 1001 Description: bbba ffff ffff Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18(L)F2X/45K50 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN Operands: -128 n 127 Operands: -128 n 127 Operation: if CARRY bit is ‘0’ (PC) + 2 + 2n PC Operation: if NEGATIVE bit is ‘0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: n 1110 Description: 0011 nnnn nnnn Encoding: 1110 If the CARRY bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18(L)F2X/45K50 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if OVERFLOW bit is ‘0’ (PC) + 2 + 2n PC Operation: if ZERO bit is ‘0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: n 1110 Description: 0101 nnnn nnnn Encoding: 1110 If the OVERFLOW bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18(L)F2X/45K50 BRA Unconditional Branch BSF Syntax: BRA Syntax: BSF Operands: -1024 n 1023 Operands: 0 f 255 0b7 a [0,1] n Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
PIC18(L)F2X/45K50 BTFSC Bit Test File, Skip if Clear BTFSS Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Bit Test File, Skip if Set Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18(L)F2X/45K50 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if OVERFLOW bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: 0111 Description: Words: Cycles: Encoding: bbba ffff ffff Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18(L)F2X/45K50 BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} Operands: -128 n 127 Operands: Operation: if ZERO bit is ‘1’ (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (Status) STATUSS, (BSR) BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the ZERO bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18(L)F2X/45K50 CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] Operation: 000h f 1Z Status Affected: Z Encoding: f {,a} 0110 Description: 101a ffff ffff Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 27.2.
PIC18(L)F2X/45K50 COMF Complement f CPFSEQ Compare f with W, skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) dest Status Affected: N, Z Encoding: 0001 11da ffff ffff Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
PIC18(L)F2X/45K50 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) –W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 Description: Words: f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of
PIC18(L)F2X/45K50 DAW Decimal Adjust W Register DECF Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then (W<7:4>) + 6 + DC W<7:4>; C = 1; else (W<7:4>) + DC W<7:4> Status Affected: Decrement f Encoding: 0000 0000 0000 0000 DAW adjusts the eight-bit value
PIC18(L)F2X/45K50 DECFSZ Decrement f, skip if 0 DCFSNZ Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F2X/45K50 GOTO Unconditional Branch INCF Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 Description: 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch Increment f Encoding: 0010 2 Cycles: 2 Q1 Q2 Q3 Q4 Read literal ‘k’<7:0>, No operation
PIC18(L)F2X/45K50 INCFSZ Increment f, skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Increment f, skip if not 0 f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F2X/45K50 IORLW Inclusive OR literal with W IORWF Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 Description: 1001 kkkk kkkk The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18(L)F2X/45K50 LFSR Load FSR MOVF Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the File Select Register pointed to by ‘f’.
PIC18(L)F2X/45K50 MOVFF Move f to f MOVLB Syntax: MOVFF fs,fd Syntax: MOVLB k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Operation: (fs) fd Status Affected: None Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18(L)F2X/45K50 MOVLW Move literal to W MOVWF Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Operation: (W) f Status Affected: None Encoding: 0000 1110 kkkk kkkk Description: The eight-bit literal ‘k’ is loaded into W. Words: 1 Cycles: 1 Move W to f Encoding: 0110 Q1 Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W Example: MOVLW = ffff ffff Move data from W to register ‘f’.
PIC18(L)F2X/45K50 MULLW Multiply literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 k 255 Operands: Operation: (W) x k PRODH:PRODL 0 f 255 a [0,1] Status Affected: None Operation: (W) x (f) PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
PIC18(L)F2X/45K50 NEGF Negate f NOP No Operation Syntax: NEGF Syntax: NOP Operands: 0 f 255 a [0,1] Operands: None Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: f {,a} 0110 Description: 1 Cycles: 1 No operation Status Affected: None Encoding: 110a ffff 0000 1111 ffff Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18(L)F2X/45K50 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18(L)F2X/45K50 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: n 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18(L)F2X/45K50 RETFIE Return from Interrupt RETLW Return literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged.
PIC18(L)F2X/45K50 RETURN Return from Subroutine RLCF Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Rotate Left f through Carry Encoding: 0000 0001 001s Description: Return from subroutine.
PIC18(L)F2X/45K50 RLNCF Rotate Left f (No Carry) RRCF Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F2X/45K50 RRNCF Rotate Right f (No Carry) SETF Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: FFh f Operation: (f) dest, (f<0>) dest<7> Status Affected: None Status Affected: f {,d {,a}} Encoding: N, Z Encoding: 0100 Description: 00da ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F2X/45K50 SLEEP Enter Sleep mode SUBFWB Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-down Status bit (PD) is cleared. The Time-out Status bit (TO) is set. The Watchdog Timer and its postscaler are cleared.
PIC18(L)F2X/45K50 SUBLW Subtract W from literal SUBWF Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k – (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 Description 1000 kkkk kkkk W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18(L)F2X/45K50 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the CARRY flag (borrow) from register ‘f’ (2’s complement method).
PIC18(L)F2X/45K50 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) – 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT; Example2: 0000 0000 0000 TBLRD = = = 55h 00A356h 34h = = 34h 00A357h +* ; Before Instruction
PIC18(L)F2X/45K50 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR – No Change; if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) – 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register; Status Affected: Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After
PIC18(L)F2X/45K50 TSTFSZ Test f, skip if 0 XORLW Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: Encoding: 0110 Description: Exclusive OR literal with W 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18(L)F2X/45K50 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 f {,d {,a}} 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18(L)F2X/45K50 27.2 A summary of the instructions in the extended instruction set is provided in Table 27-3. Detailed descriptions are provided in Section 27.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 27-1 apply to both the standard and extended PIC18 instruction sets. Extended Instruction Set In addition to the standard 75 instructions of the PIC18 instruction set, PIC18(L)F2X/45K50 devices also provide an optional extension to the core CPU functionality.
PIC18(L)F2X/45K50 27.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 Operation: FSR(f) + k FSR(f) Status Affected: None Encoding: 1110 Add Literal to FSR2 and Return FSR2 + k FSR2, Operation: (TOS) PC Status Affected: 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18(L)F2X/45K50 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: 0000 0000 0001 0100 Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded.
PIC18(L)F2X/45K50 MOVSS Move Indexed to Indexed PUSHL Syntax: Syntax: PUSHL k Operands: MOVSS [zs], [zd] 0 zs 127 0 zd 127 Operands: 0k 255 Operation: ((FSR2) + zs) ((FSR2) + zd) Operation: k (FSR2), FSR2 – 1 FSR2 Status Affected: None Status Affected: None Encoding: 1st word (source) 2nd word (dest.) 1110 1111 Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register.
PIC18(L)F2X/45K50 SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 k 63 Operands: 0 k 63 f [ 0, 1, 2 ] Operation: Operation: FSR(f) – k FSRf Status Affected: None Encoding: 1110 FSR2 – k FSR2 (TOS) PC Status Affected: None 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18(L)F2X/45K50 27.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 6.7.1 “Indexed Addressing with Literal Offset”).
PIC18(L)F2X/45K50 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value
PIC18(L)F2X/45K50 27.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18(L)F2X/45K50 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18(L)F2X/45K50 28.
PIC18(L)F2X/45K50 28.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 28.
PIC18(L)F2X/45K50 28.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18(L)F2X/45K50 28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC18(L)F2X/45K50 29.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................. .-40°C to +85°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, VUSB3V3, D+, D- and MCLR) ....................... -0.
PIC18(L)F2X/45K50 FIGURE 29-1: PIC18LF2X/45K50 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL TEMPERATURE) 5.5V Voltage 5.0V 4.0V 3.6V 3.0V 2.7V 2.3V 1.8V 4 16 20 48 Frequency (MHz) Note 1: Maximum Frequency 4 MHz, 1.8V to 2.7V, -40°C to +85°C 2: Maximum Frequency 48 MHz, 2.7V to 3.6V, -40°C to +85°C FIGURE 29-2: PIC18F2X/45K50 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL TEMPERATURE) 5.5V Voltage 5.0V 4.0V 3.6V 3.0V 2.7V 2.3V 1.
PIC18(L)F2X/45K50 29.1 DC Characteristics: Supply Voltage, PIC18(L)F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C PIC18(L)F2X/45K50 Param Symbol No. D001 VDD Characteristic Supply Voltage Min PIC18LF2X/45K50 1.8 PIC18F2X/45K50 D001B VUSB3V3 USB Supply Voltage Typ Max Units Conditions — 3.6 V Regulator disabled 2.3 — 5.5 V Regulator enabled 3.0 3.3 3.
PIC18(L)F2X/45K50 29.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Param No. Device Characteristics Power-down Base Current (IPD) D006 Conditions Typ +25°C Typ +60°C Max +85°C Units 0.01 0.04 2 A 1.8V 0.01 0.06 2 A 3.0V 12 13 25 A 2.
PIC18(L)F2X/45K50 29.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/45K50 (Continued) PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Param No.
PIC18(L)F2X/45K50 29.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Param No. D020 Device Characteristics Typ Max Units Supply Current (IDD)(1),(2) 3.6 23 A -40°C 3.9 25 A +25°C 3.9 — A +60°C 3.
PIC18(L)F2X/45K50 29.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/45K50 (Continued) PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Param No. Typ Max Units D030 0.35 0.50 mA -40°C to +85°C VDD = 1.8V D031 0.45 0.65 mA -40°C to +85°C VDD = 3.0V D032 0.40 0.60 mA -40°C to +85°C VDD = 2.
PIC18(L)F2X/45K50 29.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Param No. D045 Device Characteristics Typ Supply Current (IDD)(1),(2) 0.5 18 A -40°C 0.6 18 A +25°C D046 D047 D048 D049 Note 1: 2: Max Units Conditions 0.7 — A +60°C 0.
PIC18(L)F2X/45K50 29.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/45K50 (Continued) PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Param No. Device Characteristics Typ Max Units Conditions D055 0.25 0.40 mA -40°C to +85°C VDD = 1.8V D056 0.35 0.50 mA -40°C to +85°C VDD = 3.0V D057 0.30 0.
PIC18(L)F2X/45K50 29.5 DC Characteristics: Primary Run Supply Current, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Param No. Device Characteristics Typ Max Units Supply Current (IDD)(1),(2) 0.11 0.20 mA -40°C to +85°C VDD = 1.8V D071 0.17 0.25 mA -40°C to +85°C VDD = 3.0V D072 0.15 0.
PIC18(L)F2X/45K50 29.6 DC Characteristics: Primary Idle Supply Current, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Param No. Device Characteristics Supply Current (IDD)(1),(2) D100 Typ Max Units Conditions 0.030 0.050 mA -40°C to +85°C VDD = 1.8V D101 0.045 0.065 mA -40°C to +85°C VDD = 3.
PIC18(L)F2X/45K50 . 29.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Param No. D130 Device Characteristics Typ Supply Current (IDD)(1),(2) 3.5 23 A -40°C 3.7 25 A +25°C 3.8 — A +60°C 4.0 28 A +85°C 6.2 26 A -40°C 6.
PIC18(L)F2X/45K50 29.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Param No. Device Characteristics D135 D136 D137 D138 D139 Note 1: 2: Typ Max Units Conditions 0.9 18 A -40°C 1.0 18 A +25°C 1.1 — A +60°C 1.
PIC18(L)F2X/45K50 29.8 DC Characteristics:Input/Output Characteristics, PIC18(L)F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ† Max Units Conditions — — 0.8 V 4.5V VDD 5.5V Input Low Voltage I/O PORT: D140 with TTL buffer — — 0.15 VDD V 1.8V VDD 4.5V with Schmitt Trigger buffer — — 0.2 VDD V 2.0V VDD 5.5V with I2C™ levels — — 0.
PIC18(L)F2X/45K50 29.8 DC Characteristics:Input/Output Characteristics, PIC18(L)F2X/45K50 (Continued) DC CHARACTERISTICS Param Symbol No. VOL D159 Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Min Typ† Max Units Conditions — — 0.6 V IOL = 8 mA, VDD = 5V IOL = 6 mA, VDD = 3.3V IOL = 1.8 mA, VDD = 1.8V VDD - 0.7 — — V IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.
PIC18(L)F2X/45K50 29.9 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C DC CHARACTERISTICS Param No.
PIC18(L)F2X/45K50 29.10 USB Module Specifications Operating Conditions-40°C TA +85°C (unless otherwise state) Param No. Sym Characteristic Min Typ Max Units Conditions D313 VUSB USB Voltage 3.0 — 3.6 V Voltage on VUSB3V3 pin must be in this range for proper USB operation D314 IIL Input Leakage on pin — — ±1 A VSS VPIN VDD pin athigh impedance D315 VILUSB Input Low Voltage for USB Buffer — — 0.8 V For VUSB3V3 range D316 VIHUSB Input High Voltage for USB Buffer 2.
PIC18(L)F2X/45K50 29.11 Analog Characteristics TABLE 29-1: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated) Param No.
PIC18(L)F2X/45K50 TABLE 29-3: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param No. VR01 Sym Characteristics VROUT VR02 VR voltage output to ADC VROUT VR04* VR voltage output all other modules TSTABLE * Settling Time Min Typ Max Units Comments 0.973 1.024 1.085 V 1x output, VDD 2.5V 1.946 2.048 2.171 V 2x output, VDD 2.5V 3.891 4.096 4.342 V 4x output, VDD 4.75V (PIC18F2X/45K50) 0.942 1.024 1.
PIC18(L)F2X/45K50 TABLE 29-5: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Param Symbol No. Characteristic HLVDL<3:0> Min Typ† Max Units HLVD Voltage on VDD Transition High-toLow 0000 1.69 1.84 1.99 V 0001 1.92 2.07 2.22 V 0010 2.08 2.28 2.48 V 0011 2.24 2.44 2.64 V 0100 2.34 2.54 2.74 V 0101 2.54 2.74 2.94 V 0110 2.62 2.87 3.12 V 0111 2.76 3.01 3.26 V 1000 3.00 3.
PIC18(L)F2X/45K50 29.12 AC (Timing) Characteristics 29.12.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C™ specifications only) 2. TppS 4.
PIC18(L)F2X/45K50 29.12.2 TIMING CONDITIONS The temperature and voltages specified in Table 29-6 apply to all timing specifications unless otherwise noted. Figure 29-4 specifies the load conditions for the timing specifications. TABLE 29-6: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS FIGURE 29-4: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C Operating voltage VDD range as described in Section 29.
PIC18(L)F2X/45K50 29.12.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 29-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 29-7: Param. No.
PIC18(L)F2X/45K50 TABLE 29-8: PLL CLOCK TIMING SPECIFICATIONS Param. No. Sym F10 FOSC 4xPLL Oscillator Frequency Range Characteristic Min Max Units Conditions 4 5 MHz VDD < 2.7V, -40°C to +85°C 4 12 MHz 2.7V VDD, -40°C to +85°C F10B FOSC 3xPLL Oscillator Frequency Range 4 4 MHz 2.7V VDD, -40°C to +85°C F11 FSYS 16 20 MHz VDD < 2.7V, -40°C to +85°C 16 48 MHz 2.
PIC18(L)F2X/45K50 FIGURE 29-6: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) Note: New Value Old Value 20, 21 Refer to Figure 29-4 for load conditions. TABLE 29-10: CLKO AND I/O TIMING REQUIREMENTS Param. No.
PIC18(L)F2X/45K50 FIGURE 29-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 29-4 for load conditions. FIGURE 29-8: VDD BROWN-OUT RESET TIMING BVDD 35 VBGAP = 1.2V VIVRST Enable Internal Reference Voltage Internal Reference Voltage Stable DS30684A-page 484 36 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 TABLE 29-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. Characteristic Min Typ Max Units 2 — — s 4.1 4.7 ms 1:1 prescaler TOSC = OSC1 period 30 TmcL MCLR Pulse Width (low) 31 TWDT Watchdog Timer Time-out Period (no postscaler) 3.5 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — 33 TPWRT Power-up Timer Period 54.8 64.4 74.
PIC18(L)F2X/45K50 TABLE 29-12: TIMER0 AND TIMER1/3 EXTERNAL CLOCK REQUIREMENTS Param. No. Symbol Characteristic 40 Tt0H T0CKI High Pulse Width No prescaler 41 Tt0L T0CKI Low Pulse Width No prescaler 42 Tt0P T0CKI Period Min Max Units 0.5 TCY + 20 — ns With prescaler 10 — ns 0.5 TCY + 20 — ns With prescaler With prescaler 45 Tt1H TxCKI High Time 10 — ns TCY + 10 — ns Greater of: 20 ns or (TCY + 40)/N — ns 0.
PIC18(L)F2X/45K50 TABLE 29-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param . Symbol No. 50 TccL 51 TccH Characteristic Min Max Units CCPx Input Low No prescaler Time With prescaler 0.5 TCY + 20 — ns 10 — ns CCPx Input High Time 0.
PIC18(L)F2X/45K50 TABLE 29-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0 OR 1) Param. No.
PIC18(L)F2X/45K50 FIGURE 29-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 77 75, 76 MSb In SDI 73 bit 6 - - - -1 LSb In 74 Refer to Figure 29-4 for load conditions. Note: TABLE 29-15: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0 OR 1) Param. No.
PIC18(L)F2X/45K50 FIGURE 29-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS 70 SCK (CKP = 0) 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI Note: MSb In 77 bit 6 - - - -1 LSb In 74 Refer to Figure 29-4 for load conditions. I2C™ BUS START/STOP BITS TIMING FIGURE 29-15: SCL 91 90 93 92 SDA Start Condition Note: Stop Condition Refer to Figure 29-4 for load conditions. DS30684A-page 490 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 TABLE 29-16: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18(L)F2X/45K50 TABLE 29-17: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol No. 100 THIGH Characteristic Clock High Time Min Max Units Conditions 100 kHz mode 4.0 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Must operate at a minimum of 10 MHz 1.5 TCY — 100 kHz mode 4.7 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Must operate at a minimum of 10 MHz SSP Module 101 TLOW Clock Low Time 1.5 TCY — — 1000 ns 20 + 0.
PIC18(L)F2X/45K50 FIGURE 29-17: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 29-4 for load conditions. TABLE 29-18: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18(L)F2X/45K50 TABLE 29-19: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.
PIC18(L)F2X/45K50 FIGURE 29-19: TX/CK RX/DT EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING pin 121 121 pin 120 Note: 122 Refer to Figure 29-4 for load conditions. TABLE 29-20: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. No.
PIC18(L)F2X/45K50 TABLE 29-22: A/D CONVERTER CHARACTERISTICS:PIC18(L)F2X/45K50 Standard Operating Conditions (unless otherwise stated) Operating temperature Tested at +25°C PIC18(L)F2X/45K50 Param. Symbol No. Characteristic Min Typ Max Units Conditions A01 NR Resolution — — 10 bits VREF 3.0V A03 EIL Integral Linearity Error — ±0.5 ±1 LSb VREF = 3.0V A04 EDL Differential Linearity Error — ±0.5 ±1 LSb VREF 3.0V A06 EOFF Offset Error — ±0.7 ±2 LSb VREF 3.
PIC18(L)F2X/45K50 TABLE 29-23: A/D CONVERSION REQUIREMENTS (PIC18(L)F2X/45K50) Standard Operating Conditions (unless otherwise stated) Operating temperature Tested at +25°C Param. Symbol No. Characteristic Min Typ Max Units 130 TAD A/D Clock Period 1 — 25 s 131 TCNV Conversion Time (not including acquisition time) (Note 1) 12 — 12 TAD 132 TACQ Acquisition Time (Note 2) 1.
PIC18(L)F2X/45K50 NOTES: DS30684A-page 498 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 30.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 NOTES: DS30684A-page 500 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 31.0 PACKAGING INFORMATION 31.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC18F25K50 -I/SP e3 0810017 28-Lead SOIC (7.50 mm) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP (5.30 mm) Example PIC18F25K50 -I/SO e3 0810017 Example PIC18F25K50 -I/SS e3 0810017 Legend: XX...
PIC18(L)F2X/45K50 Package Marking Information (Continued) 28-Lead QFN (6x6 mm) PIN 1 XXXXXXXX XXXXXXXX YYWWNNN Example PIN 1 18F25K50 -I/ML e3 0810017 40-Lead PDIP (600 mil) XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F45K50 -I/P e3 0810017 40-Lead UQFN (5x5x0.5 mm) PIN 1 Example PIN 1 PIC18F 45K50 -I/MV e 0810017 3 Legend: XX...
PIC18(L)F2X/45K50 Package Marking Information (Continued) 44-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: Example 18F45K50 -I/PT e3 0810017 Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free.
PIC18(L)F2X/45K50 31.2 Package Details The following sections give the technical details of the packages. ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8.
PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30684A-page 506 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 #$ ! " % &' % 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 1 2 b NOTE 1 e c A2 A φ A1 L L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; < & : 8 & = = ? < & # %% = = : > #& . < < # # 4 > #& .
PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 DS30684A-page 510 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 * + , ! - . )/) *+! 0 # '&& 1 - # ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 ( ) DS30684A-page 512 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30684A-page 514 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 (( 2# ! " * + 3 2 4 /4 /4 , ' 2*+ 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 6 &! ' ! 9 ' &! 7"') % 9 #! 99 . .
PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 NOTES: DS30684A-page 518 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 APPENDIX A: REVISION HISTORY Revision A (August 2012) Initial release. 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. TABLE B-1: Features DEVICE DIFFERENCES (1) PIC18F24K50 PIC18LF24K50 PIC18F25K50 PIC18LF25K50 PIC18F45K50 PIC18LF45K50 16384 16384 32768 32768 32768 32768 VDD Range 2.3V to 5.5V 1.8V to 3.6V 2.3V to 5.5V 1.8V to 3.6V 2.3V to 5.5V 1.8V to 3.
PIC18(L)F2X/45K50 INDEX A A/D Analog Port Pins, Configuring................................... 312 Associated Registers ................................................ 312 Conversions .............................................................. 303 Converter Characteristics ......................................... 496 Discharge.................................................................. 304 Selecting and Configuring Acquisition Time ............. 300 Absolute Maximum Ratings ......................
PIC18(L)F2X/45K50 BTFSS............................................................................... 418 BTG................................................................................... 419 BZ...................................................................................... 420 C C Compilers MPLAB C18 .............................................................. 456 CALL ................................................................................. 420 CALLW.................................
PIC18(L)F2X/45K50 Measuring Time with................................................. 333 Operation .................................................................. 324 Operation During Idle Mode...................................... 334 Operation During Sleep Mode .................................. 334 Customer Change Notification Service ............................. 531 Customer Notification Service........................................... 531 Customer Support .......................................
PIC18(L)F2X/45K50 Synchronous Slave Mode Associated Registers, Receive ......................... 297 Reception.......................................................... 297 Transmission..................................................... 295 Extended Instruction Set ADDFSR ................................................................... 448 ADDULNK ................................................................. 448 and Using MPLAB Tools ........................................... 454 CALLW............
PIC18(L)F2X/45K50 CPFSLT .................................................................... 423 DAW.......................................................................... 424 DCFSNZ ................................................................... 425 DECF ........................................................................ 424 DECFSZ.................................................................... 425 Extended Instruction Set........................................... 447 General Format......
PIC18(L)F2X/45K50 P P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/ PWM (ECCP) ............................................................ 192 Packaging Information ...................................................... 501 Marking ..................................................................... 501 PIE Registers .................................................................... 119 PIE1 Register .................................................................... 126 PIE2 Register ...................
PIC18(L)F2X/45K50 EECON1 (Data EEPROM Control 1) ................ 101, 110 HLVDCON (High/Low-Voltage Detect Control)......... 379 INTCON (Interrupt Control)....................................... 120 INTCON2 (Interrupt Control 2).................................. 121 INTCON3 (Interrupt Control 3).................................. 122 IPR1 (Peripheral Interrupt Priority 1)......................... 129 IPR2 (Peripheral Interrupt Priority 2)......................... 130 IPR3 (Peripheral Interrupt Priority)....
PIC18(L)F2X/45K50 Reads and Writes in 16-Bit Mode ............................. 162 Source Edge Select (T0SE Bit)................................. 162 Source Select (T0CS Bit) .......................................... 162 Switching Prescaler Assignment............................... 163 Timer1 ............................................................................... 165 Associated registers.................................................. 176 Asynchronous Counter Mode ...............................
PIC18(L)F2X/45K50 Top-of-Stack Access ........................................................... 78 TSTFSZ ............................................................................ 445 Two-Speed Clock Start-up Mode ........................................ 45 Two-Speed Start-up .......................................................... 385 Two-Word Instructions Example Cases........................................................... 83 TXREG................................................................
PIC18(L)F2X/45K50 NOTES: DS30684A-page 530 2012 Microchip Technology Inc.
PIC18(L)F2X/45K50 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC18(L)F2X/45K50 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC18(L)F2X/45K50 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](2) PART NO.
PIC18(L)F2X/45K50 NOTES: DS30684A-page 534 2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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