Information

 2008-2013 Microchip Technology Inc. DS80000425K-page 7
PIC18F24K20/25K20/44K20/45K20
19. Module: POR
The POR may release around 0.8V (below the
POR rearm voltage of 1.2V, nominal) when V
DD
rises from below 0.60V (when BOR is not enabled)
or 0.33V (when BOR is enabled).
Work around
Use Power-up Timer when operating with the EC,
EXTRC or HFINTOSC oscillator modes. Ensure
that VDD rise time is less than the Power-up Timer
time.
Affected Silicon Revisions
20. Module: POR
The part may hang in the Reset state when VDD
rises to the operating range at a rate faster than
7500V per second. Recovery from the hung state
is possible only by first lowering VDD to below 0.3V,
followed by raising V
DD to the operating range.
Work around
Slow VDD rise time by adding series resistance
between the voltage supply and the V
DD pin and
increasing the V
DD bypass capacitance. VDD
bypassing should remain on the pin side of the
series resistor.
Affected Silicon Revisions
21. Module: Clocks
EC mode operation is limited to a maximum of
48 MHz (Rev. A4 and A7 only).
Work around
Divide external clock by 4 and use HS-PLL Clock
mode for external clocking above 48 MHz.
Affected Silicon Revisions
22. Module: Comparators
When the CxON bit is clear, the output from the
comparator will be properly forced to zero, but the
CxPOL bit will improperly have no effect on the
CxOUT bit. This prevents presetting the compara-
tor change-on-interrupt mismatch latches as
described in the data sheet.
Work around
Configure one of the unused comparator input
channels as a digital output. Use that digital output
to manipulate the comparator output to the desired
CxOUT non-interrupt level. When the comparator
is then set to the desired inputs, the mismatch
latches will be preset to the non-interrupt level and
the CxIF flag can then be cleared.
Affected Silicon Revisions
23. Module: Data EEPROM Memory
The write/erase endurance of Data EE Memory is
limited to 10K cycles.
Work around
Use error correction method that stores data in
multiple locations.
Affected Silicon Revisions
24. Module: Program Flash Memory
The write/erase endurance of the PFM is limited to
1K cycles when V
DD is above 3V. Endurance
degrades when V
DD is below 3V.
Work around
For data tables in program Flash memory use
error correction method that stores data in multiple
locations.
Affected Silicon Revisions
0xA 0xC
0xE
0x11
0x16 0x18 0x19
0x1B 0x1C
XXXX
0xA 0xC
0xE
0x11
0x16 0x18 0x19
0x1B 0x1C
XXXX
0xA 0xC
0xE
0x11
0x16 0x18 0x19
0x1B 0x1C
XX
0xA 0xC
0xE
0x11
0x16 0x18 0x19
0x1B 0x1C
XXXX
0xA 0xC
0xE
0x11
0x16 0x18 0x19
0x1B 0x1C
XXXXXXX
0xA 0xC
0xE
0x11
0x16 0x18 0x19
0x1B 0x1C
XXXXXXX