Information
2008-2013 Microchip Technology Inc. DS80000425K-page 3
PIC18F24K20/25K20/44K20/45K20
EUSART Asynchronous
Receive mode
26. RCIDL bit may stay low
improperly.
X X X X
PORTB Interrupts Interrupt-on-
Change
27. False interrupt when setting
interrupt enable.
X X X XXXXXX
ADC ADC
Conversion
28. ADC conversion may be limited
to half scale.
X X X XXXX
ECCP Full-Bridge
mode
29. Wrong dead-band time.
XXXXX
ECCP Full-Bridge
mode
30. Wrong signal start time.
XXXXX
MSSP SPI SPI Clock 31. Improper SCK output.
XXXXX
MSSP SPI SPI Master 32. Improper sampling of last bit. XXXXX
MSSP SPI SPI Master 33. Improper handling of write
collision.
XXXXX
MSSP I
2
C™ I
2
C™ Master 34. Improper handling of Stop event. XXXXX
EUSART OERR Flag 35. Clearing SPEN bit does not clear
OERR flag.
XXXXX
EUSART BAUDCTL 36. RCIDL bit may stay low
improperly.
XXXXX
PORTB Interrupts Interrupt-on-
Change
37. False interrupt when waking
from Sleep.
XXXXX
BOR Reset 38. Reset on configuring the analog
comparators to the FVR.
X X X XXXXXX
Wake-up from
Low-Power Sleep
mode
Wake-up
Sources
39. Device may not wake-up under
specific conditions.
X X X XXXXXX
Low-Voltage
Detect
LVD in Sleep 40. LVD erroneously triggers upon
wake-up from Sleep if band gap
is disabled in Sleep mode.
X X X XXXXXX
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
A4
A7
A9
AB
A4
A7
A8
AE
AF
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
2: Shaded cells in this table indicate older device revisions that are no longer in production.