Information

PIC18F24K20/25K20/44K20/45K20
DS80000425K-page 10  2008-2013 Microchip Technology Inc.
35. Module: EUSART
The OERR flag of the RCSTA register is reset only
by clearing the CREN bit of the RCSTA register or
by a device Reset. Clearing the SPEN bit of the
RCSTA register does not clear the OERR flag.
Work around
Clear the OERR flag by clearing the CREN bit
instead of clearing the SPEN bit.
Affected Silicon Revisions
36. Module: EUSART
In Asynchronous Receive mode, the RCIDL bit of
the BAUDCON register will properly go low when
an invalid Start bit less than 1/16th of a bit time is
received. The RCIDL bit will then properly go high
1/8th of a bit time later. However, if another invalid
Start bit occurs less than 1 bit time after the leading
edge of the first invalid Start bit, then the RCIDL bit
will improperly stay high then improperly go low
one bit time later. The RCIDL bit will then stay low
improperly until a valid Start bit is received.
Work around
When monitoring the RCIDL bit, measure the
length of time between the RCIDL going low and
the RCIF flag going high. If this time is greater than
one character time, then restore the RCIDL bit by
resetting the EUSART module. The EUSART
module is reset when the SPEN bit of the RCSTA
register is cleared.
Affected Silicon Revisions
37. Module: Interrupt-on-Change
When any interrupt-on-change is enabled and the
corresponding input is high, then waking from
Sleep by a source other than interrupt-on-change
may cause the RBIF interrupt flag bit to become
set improperly.
Work around
1. Use the INTx interrupt in lieu of interrupt-on-
change.
Or
2. Store the state of the PORTB inputs before
entering Sleep. Upon waking, if an RBIF is
detected, then compare the PORTB levels
with those stored. If they are the same, then
clear and ignore the RBIF interrupt.
Affected Silicon Revisions
38. Module: BOR
An unexpected Brown-out Reset may occur when
enabling the comparator with the Fixed Voltage
Reference (FVR) selected as the V
IN+ input.
Work around
Disconnect the FVR from the VIN+ comparator
inputs prior to enabling the comparator and then
reconnect it after enabling the comparator.
Affected Silicon Revisions
0xA 0xC
0xE
0x11
0x16 0x18 0x19
0x1B
0x1C
XXXXX
0xA 0xC
0xE
0x11
0x16 0x18 0x19
0x1B 0x1C
XXXXX
0xA 0xC
0xE
0x11
0x16 0x18 0x19
0x1B 0x1C
XXXXX
0xA 0xC
0xE
0x11
0x16 0x18 0x19
0x1B 0x1C
XXXXXXXXX