Datasheet

PIC18F24/25/44/45K20
DS80366G-page 2 © 2009 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected Revisions
(1)
A4 A7 A9 AB
ECCP CCP1CON 1. Changing CCP1M bits may cause capture
of Timer1 value.
XXXX
ECCP Full Bridge
Mode
2. Direction change issue. X X X X
MSSP SPI SPI Clock 3. Shortened SPI high time. X X X X
MSSP I
2
C™ Slew Rate 4. Slow slew rate when SLRCON<2> is set. X X X X
ADC Offset 5. Time dependent on offset. X X X X
MSSP I
2
C Receiving 6. Address may be received as data. X X X X
MSSP I
2
C Master Mode 7. Master mode not functional. X
MSSP SPI SPI Master 8. Improper sampling of last bit. X X X X
MSSP SPI SPI Master 9. SSPBUF improperly reloads on SS pin
transitions.
XXXX
MSSP SPI SPI Master 10. Improper extra pulse on SCK pin. X X X X
EUSART Synchronous
Master Mode
11. Duty cycle of CK output is skewed when
SPBRG is odd.
XXXX
EUSART Synchronous
Master Mode
12. LS bit corruption during transmission
when SPBRG = 3.
XXXX
EUSART Synchronous
Master Mode
13. Clock fails to stop at end of character
transmission when SPBRG = 0.
XXXX
Internal Fixed
Voltage Refer-
ence (FVR)
— 14. FVRST bit activates prematurely. X X
High Low Voltage
Detect (HLVD)
— 15. IVRST bit activates prematurely. X X
BOR FVR 16. Unexpected BOR occurrence. X X
System Clocks — 17. HFINTOSC output accuracy. X X X X
POR/BOR — 18. Unexpected code execution at low V
DD.XXXX
POR — 19. Premature POR release. X X X X
POR — 20. POR may become stuck. X X X X
Clocks EC Mode 21. 48 MHz maximum frequency. X X
Comparators Interrupt-on-
Change
22. Presetting interrupt-on-change issue. X X X X
Data EEPROM
Memory
Endurance 23. Endurance is limited to 10K cycles. X X X X
Program Flash
Memory
Endurance 24. Endurance is limited to 1K cycles. X X X X
Configuration Bits CONFIG3H 25. HFOFST bit erases to ‘0’ instead of ‘1’. X X X X
EUSART Asynchronous
Receive Mode
26. RCIDL bit may stay low improperly. X X X X
PORTB Interrupt-on-
Change
27. False interrupt when setting interrupt
enable.
XXXX
ADC ADC
Conversion
28. ADC conversion may be limited to half
scale.
XXXX
Note 1: Only those issues indicated in the last column apply to the current silicon revision.