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PIC18F24/25/44/45K20

The PIC18F24/25/44/45K20 family devices that you

have received conform functionally to the current Device

Data Sheet (DS41303F), except for the anomalies

described in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC18F24/25/44/45K20 silicon.

Data Sheet clarifications and corrections start on page 8,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2 programmer/

debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

onfigure>Select Device, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger

>Select Tool).

4. Perform a “Connect” operation to the device

(Debugger>Connect

). Depending on the

development tool used, the part number and

Device Revision ID value appear in the Output

window.

The DEVREV values for the various PIC18F24/25/44/

45K20 silicon revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all specified revisions of

silicon.

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

(11-bit)

Revision ID for Silicon Revision

(2)

(5-bit)

A4 A7 A9 AB

PIC18F24K20 105h

0xA 0xC 0xE 0x11

PIC18F25K20 103h

0xA 0xC 0xE 0x11

PIC18F44K20 104h

0xA 0xC 0xE 0x11

PIC18F45K20 102h

0xA 0xC 0xE 0x11

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration

memory space. They are shown in hexadecimal in the format “DEVID:DEVREV”.

2: Refer to the “PIC18F2XK20/4XK20 Flash Memory Programming Specification” (DS41297) for detailed

information on Device and Revision IDs for your specific device.

3: If your device contains a revision ID code that is greater than 0x11, please refer to DS80425 for silicon

errata and data sheet clarifications.

PIC18F24/25/44/45K20 Device IDs Rev. 0xA Through 0x11

Silicon Errata and Data Sheet Clarification

Summary of content (12 pages)

PAGE 1
PIC18F24/25/44/45K20 PIC18F24/25/44/45K20 Device IDs Rev. 0xA Through 0x11 Silicon Errata and Data Sheet Clarification The PIC18F24/25/44/45K20 family devices that you have received conform functionally to the current Device Data Sheet (DS41303F), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
PAGE 2
PIC18F24/25/44/45K20 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A4 A7 A9 AB ECCP CCP1CON 1. Changing CCP1M bits may cause capture of Timer1 value. X X X X ECCP Full Bridge Mode 2. Direction change issue. X X X X SPI Clock 3. Shortened SPI high time. X X X X MSSP I C™ Slew Rate 4. Slow slew rate when SLRCON<2> is set. X X X X ADC Offset 5. Time dependent on offset. X X X X MSSP I2C Receiving 6.
PAGE 3
PIC18F24/25/44/45K20 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all specified revisions of silicon. 4. Module: MSSP I2C™ Slew rate is slower than I2C specifications when the SLRCON<2> bit is set. Work around Clear SLRCON<2> bit when using the I2C peripheral. 1. Module: ECCP Changing the CCP1M<3:0> bits of CCP1CON may cause the CCPR1H and CCPR1L registers to capture the value of Timer1. Work around Halt Timer1 before changing ECCP mode.
PAGE 4
PIC18F24/25/44/45K20 8. Module: MSSP SPI In SPI Master mode, when the CKE bit is cleared and the SMP bit is set, the last bit of the incoming data stream (bit 0) at the SDI pin will not be sampled properly. Work around 12. Module: EUSART In Synchronous Master mode, when the SPBRG is set to 3 and the TXREG is written while the previous character is still in the TX shift register, the LS bit of the TXREG character may be corrupted during transmission. Work around None.
PAGE 5
PIC18F24/25/44/45K20 15. Module: High Low Voltage Detect (HLVD) The IVRST bit of the HLVDCON register activates prematurely (Rev. A4 and A7 only). Work around Wait an additional 20 µs after IVRST is sensed high before using the fixed voltage reference. Enable the FVR by setting the FVREN bit of the CVRCON2 register before activating any peripheral that automatically enables the FVR. Peripherals that automatically enable the FVR include the Brown-out Reset, the High/Low Voltage Detect, and the HFINTOSC.
PAGE 6
PIC18F24/25/44/45K20 21. Module: Clocks 24. Module: Program Flash Memory EC Mode operation is limited to a maximum of 48 MHz (Rev. A4 and A7 only). Work around Divide external clock by 4 and use HS-PLL Clock mode for external clocking above 48 MHz. Affected Silicon Revisions A4 A7 X X A9 AB 22. Module: Comparators When the CxON bit is clear, the output from the comparator will be properly forced to zero, but the CxPOL bit will improperly have no effect on the CxOUT bit.
PAGE 7
PIC18F24/25/44/45K20 27. Module: PORTB Work around Setting a PORTB Interrupt-on-change enable bit of the IOCB register while the corresponding PORTB input is high will cause an RBIF interrupt. Work around Set the IOCB bits to the desired configuration then read PORTB to clear the mismatch latches. Finally, clear the RBIF bit before setting the RBIE bit. Affected Silicon Revisions A4 A7 A9 AB X X X X 1.
PAGE 8
PIC18F24/25/44/45K20 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS41303F): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. None. DS80366G-page 8 © 2009 Microchip Technology Inc.
PAGE 9
PIC18F24/25/44/45K20 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (02/2008) First revision of this document. Rev B Document (05/12/08) Added Module 20: POR, updating subsequent numbering. Updated Module 5: ADC, Work around description. Added Module 8 MSSP I2C, updating subsequent numbering. Revised Module 22: Clocks, added silicon revs. Rev C Document (08/2008) Revised Module 22; Added Modules 27 and 28. Rev D Document (01/2009) Revised Module 21; Added Module 29.
PAGE 11
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 12
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