Information

 2011 Microchip Technology Inc. DS80436D-page 3
PIC18F46J50 FAMILY
Silicon Errata Issues
1. Module: Master Synchronous Serial Port
(MSSP1)
If the LATB<5> or LATB<4> bit is set, the
MSSP1 module will not work correctly in the
I
2
C™ modes. If both LATB<5> and LATB<4>
are clear, the module will work normally.
Work around
Clear the bits, LATB<5:4>, prior to enabling the
MSSP1 module in an I
2
C mode. Keep these bits
clear while using the module.
For operation in I
2
C modes, the TRISB<5:4>
bits should be set.
Affected Silicon Revisions
2. Module: Master Synchronous Serial Port
(MSSP)
In extremely rare cases, when configured for I
2
C™
slave reception, the MSSP module may not receive
the correct data. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPxBUF) is not
read within a window after the SSPxIF interrupt
has occurred.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
2
C slave reception, enable the
clock stretching feature.
This is done by setting the SEN bit
(SSPxCON2<0>).
• Each time the SSPxIF is set, read the
SSPxBUF before the first rising clock edge of
the next byte being received.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (Rev. A4).
A2
A4
X
A2 A4
X
X