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 2011 Microchip Technology Inc. DS80436D-page 1

PIC18F46J50 FAMILY

The PIC18F46J50 family devices that you have received

conform functionally to the current Device Data Sheet

(DS39931D), except for the anomalies described in this

document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC18F46J50 family silicon.

Data Sheet clarifications and corrections start on page 8,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2 programmer/

debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

onfigure>Select Device, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger

>Select Tool).

4. Perform a “Connect” operation to the device

(Debugger

>Connect). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The DEVREV values for the various PIC18F46J50 family

silicon revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (Rev. A4).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

A2 A4

PIC18F24J50 4C0Xh

2h 4h

PIC18F25J50 4C2Xh

PIC18F26J50 4C4Xh

PIC18F44J50 4C6Xh

PIC18F45J50 4C8Xh

PIC18F46J50 4CAXh

PIC18LF24J50 4CCXh

PIC18LF25J50 4CEXh

PIC18LF26J50 4D0Xh

PIC18LF44J50 4D2Xh

PIC18LF45J50 4D4Xh

PIC18LF46J50 4D6Xh

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration

memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.

2: Refer to the “PIC18F2XJXX/4XJXX Family Flash Microcontroller Programming Specification” (DS39687)

for detailed information on Device and Revision IDs for your specific device.

PIC18F46J50 Family

Silicon Errata and Data Sheet Clarification

Summary of content (12 pages)

PAGE 1
PIC18F46J50 FAMILY PIC18F46J50 Family Silicon Errata and Data Sheet Clarification The PIC18F46J50 family devices that you have received conform functionally to the current Device Data Sheet (DS39931D), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
PAGE 2
PIC18F46J50 FAMILY TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A2 A4 MSSP I2 C™ Modes 1. Must keep LATB<5:4> bits clear. MSSP I2C Slave 2. Module may not receive the correct data if there is a delay in reading SSPxBUF after SSPxIF interrupt. X X X EUSART Enable/ Disable 3. If interrupts are enabled, a 2 TCY delay needed after re-enabling the module. X X A/D FOSC/2 Clock 4.
PAGE 3
PIC18F46J50 FAMILY Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (Rev. A4). 1. Module: Master Synchronous Serial Port (MSSP1) 2. Module: Master Synchronous Serial Port (MSSP) In extremely rare cases, when configured for I2C™ slave reception, the MSSP module may not receive the correct data.
PAGE 4
PIC18F46J50 FAMILY 3. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) In rare situations, when interrupts are enabled, unexpected results may occur if: Work around Add a 2 TCY delay after any instruction that reenables the EUSART module (sets SPEN = 1). Refer to Example 1.
PAGE 5
PIC18F46J50 FAMILY 4. Module: 10-Bit Analog-to-Digital Converter (ADC) When the A/D conversion clock select bits are set for FOSC/2 (ADCON1<2:0> = 000), the Integral Linearity Error (EIL) parameter (A03) and Differential Linearity Error (EDL) parameter (A04) may exceed data sheet specifications. Work around Select one of the alternate AD clock sources shown in Table 3. The EIL and EDL parameters are met for the other clocking options. 5.
PAGE 6
PIC18F46J50 FAMILY 6. Module: Low-Power Modes (Deep Sleep) Entering Deep Sleep mode takes approximately 2 TCY, following the SLEEP instruction. Wake-up events that occur during this Deep Sleep entry period may not generate a wake-up event. instruction before the SLEEP instruction eliminates the 2 TCY window where wake-up events could be missed. Work around Before using this work around, users should check their device’s revision ID bits to verify that they have the A4 silicon.
PAGE 7
PIC18F46J50 FAMILY 7. Module: DC Characteristics (Supply Voltage) The minimum operating voltage (VDD) parameter (D001) for “F” devices is 2.25V. For “LF” devices (such as the PIC18LF46J50), the minimum rated VDD operating voltage is 2.0V. Work around None. Affected Silicon Revisions A2 A4 X 9. Module: Charge Time Measurement Unit (CTMU) On an “F” device, the CTMU current source will stop sourcing current if the applied VDD voltage falls below the LVDSTAT (WDTCON<6>) threshold (2.45V nominal).
PAGE 8
PIC18F46J50 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the Device Data Sheet (DS39931D): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Special Features (CONFIG2L) The “T1DIG” feature mentioned in the Device Data Sheet (DS39931D) is not implemented in this device family.
PAGE 9
PIC18F46J50 FAMILY APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (2/2009) First release of this document. Silicon issues 1 (T1DIG), 2-3 (MSSP), 4 (EUSART), 5 (ADC), 6 (PMP), 7 (Deep Sleep), 8 (Supply Voltage). Rev B Document (5/2009) Added silicon issues 9 (Band Gap Reference) and 10 (Charge Time Measurement Unit – CTMU). Rev C Document (1/2010) Converted existing document for the A2 silicon revision to the new, combined format.
PAGE 10
PIC18F46J50 FAMILY NOTES: DS80436D-page 10  2011 Microchip Technology Inc.
PAGE 11
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 12
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