Information

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 8-Bit 48 MHz I/O number 16

 2009-2013 Microchip Technology Inc. DS80000435K-page 1

PIC18F46J11

The PIC18F46J11 family devices that you have received

conform functionally to the current Device Data Sheet

(DS39932D), except for the anomalies described in this

document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC18F46J11 family silicon.

Data Sheet clarifications and corrections start on page 9,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level

using MPLAB IDE in conjunction with a hardware

debugger:

1. Using the appropriate interface, connect the

device to the hardware debugger.

2. Open an MPLAB IDE project.

3. Configure the MPLAB IDE project for the

appropriate device and hardware debugger.

4. Based on the version of MPLAB IDE you are

using, do one of the following:

a) For MPLAB IDE 8, select Programmer >

Reconnect.

b) For MPLAB X IDE, select Window >

Dashboard and click the Refresh Debug

Tool Status icon ( ).

5. Depending on the development tool used, the

part number and Device Revision ID value

appear in the Output window.

The DEVREV values for the various PIC18F46J11

family silicon revisions are shown in Tabl e 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the issues

indicated in the last column of Ta b le 2 apply

to the current silicon revision (A4).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

A2 A4

PIC18F24J11 0x26Ch

2h 4h

PIC18F25J11 0x26Dh

PIC18F26J11 0x26Eh

PIC18F44J11 0x26Fh

PIC18F45J11 0x270h

PIC18F46J11 0x271h

PIC18LF24J11 0x272h

PIC18LF25J11 0x273h

PIC18LF26J11 0x274h

PIC18LF44J11 0x275h

PIC18LF45J11 0x276h

PIC18LF46J11 0x277h

Note 1: The Device IDs (DEVID and REVID) are located at the last two implemented addresses of configuration memory space.

They are shown in hexadecimal in the format, “DEVID:REVID”.

2: Refer to the “PIC18F2XJXX/4XJXX Family Flash Microcontroller Programming Specification” (DS39687) for detailed

information on Device and Revision IDs for your specific device.

PIC18F46J11 Family

Silicon Errata and Data Sheet Clarification

Summary of content (13 pages)

PAGE 1
PIC18F46J11 PIC18F46J11 Family Silicon Errata and Data Sheet Clarification The PIC18F46J11 family devices that you have received conform functionally to the current Device Data Sheet (DS39932D), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with a hardware debugger: 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1.
PAGE 2
PIC18F46J11 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A2 A4 MSSP I2C™ Mode 1. If a Stop condition occurs in the middle of an address or data reception, there will be issues with the SCL clock stream and RCEN bit. X X MSSP I2C™ Slave Reception 2. In I2C™ slave reception, the module may have problems receiving correct data. X X EUSART Enable/ Disable 3.
PAGE 3
PIC18F46J11 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A4). 1.
PAGE 4
PIC18F46J11 3. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) In rare situations when interrupts are enabled, unexpected results may occur if: • The EUSART is disabled (SPEN bit (RCSTAx<7>) = 0) • The EUSART is re-enabled (RCSTAx<7> = 1) • A two-cycle instruction is executed immediately after setting SPEN, CREN or TXEN = 1 EXAMPLE 1: Work around Add a 2 TCY delay after any instruction that re-enables the EUSART module (sets SPEN, CREN or TXEN = 1). See Example 1.
PAGE 5
PIC18F46J11 6. Module: Low-Power Modes (Deep Sleep) Entering Deep Sleep mode takes approximately 2 TCY, following the SLEEP instruction. Wake-up events that occur during this Deep Sleep entry period may not generate a wake-up event. Work around If using the RTCC alarm for Deep Sleep wake-up, code should only enter Deep Sleep mode when the RTCC Value Registers Read Synchronization bit (RTCCFG<4>) is clear.
PAGE 6
PIC18F46J11 7. Module: DC Characteristics (Supply Voltage) The minimum operating voltage (VDD) parameter (D001) for the F devices is 2.25V. For the LF devices (such as PIC18LF46J11), the minimum rated VDD operating voltage is 2.0V. Work around None. Affected Silicon Revisions A2 A4 X 8. Module: Special Features (T1DIG) The T1DIG Configuration bit (CONFIG2L<3>) function is not implemented. Effectively, T1DIG is ‘0’ regardless of the value programmed into the bit. Work around None. 10.
PAGE 7
PIC18F46J11 11. Module: Charge Time Measurement Unit (CTMU) On the F devices, the CTMU current source will stop sourcing current if the applied VDD voltage falls below the LVDSTAT (WDTCON<6>) threshold (2.45V nominal). When VDD is above the LVDSTAT threshold, the CTMU will function normally. This issue does not apply to the LF devices. The current source will continue functioning normally at all rated voltages for these devices. Work around None. Affected Silicon Revisions A2 A4 X 12.
PAGE 8
PIC18F46J11 13. Module: Timer1/Timer3 When the timer is operated in Asyncronous External Input mode, unexpected interrupt flag generation may occur if an external clock edge arrives too soon following a firmware write to TMRxH:TMRxL register. An unexpected interrupt flag may also occur when enabling the module or switching from Synchronous to Asynchronous mode. Work around This issue only applies when operating the timer in Asynchronous mode.
PAGE 9
PIC18F46J11 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39932D): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Special Features of the CPU On the 32K Flash devices (PIC18F45J11, PIC18F25J11), it is necessary to write WPFP5 (CONFIG4L<5>) with ‘0’ to maintain proper operation of the write-protect feature.
PAGE 10
PIC18F46J11 The corrected data sheet definition for Register 26-7: REGISTER 26-7: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 WPCFG WPEND WPFP5(2) WPFP4(3) WPFP3 WPFP2 WPFP1 WPFP0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WPCFG: Write/Erase Protect Configuration Region Select
PAGE 11
PIC18F46J11 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (2/2009) First release of this document. Silicon issues 1-2 (MSSP), 3 (EUSART), 4 (ADC), 5 (PMP), 6 (Deep Sleep), 7 (Supply Voltage). Rev B Document (3/2009) Modified silicon issues 1 (MSSP) and 3 (EUSART), and added silicon issue 8 (Special Features – T1DIG). Rev C Document (4/2009) Added silicon issue 9 (Master Synchronous Serial Port (MSSP) – Port 1). Rev D Document (6/2009) Revised document to new format.
PAGE 12
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 13
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.