Datasheet
PIC18F45J10 FAMILY
DS39682E-page 64 © 2009 Microchip Technology Inc.
SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 49, 198
SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 49, 198
RCREG EUSART Receive Register 0000 0000 49, 205
TXREG EUSART Transmit Register xxxx xxxx 49, 203
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 49, 196
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 49, 195
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 49, 72
EECON1
— — — FREE WRERR WREN WR — ---0 x00- 49, 74
IPR3 SSP2IP BCL2IP
— — — — — — 11-- ---- 49, 94
PIR3 SSP2IF BCL2IF
— — — — — — 00-- ---- 49, 90
PIE3 SSP2IE BCL2IE
— — — — — — 00-- ---- 49, 92
IPR2 OSCFIP CMIP
— —BCL1IP— — CCP2IP 11-- 1--1 49, 93
PIR2 OSCFIF CMIF
— —BCL1IF— — CCP2IF 00-- 0--0 49, 89
PIE2 OSCFIE CMIE
— —BCL1IE— — CCP2IE 00-- 0--0 49, 91
IPR1 PSPIP
(2)
ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 49, 92
PIR1 PSPIF
(2)
ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 49, 88
PIE1 PSPIE
(2)
ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 49, 91
TRISE
(2)
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 50, 112
TRISD
(2)
PORTD Data Direction Control Register 1111 1111 50, 107
TRISC PORTC Data Direction Control Register 1111 1111 50, 104
TRISB PORTB Data Direction Control Register 1111 1111 50, 101
TRISA
— — TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 --1- 1111 50, 98
SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 50, 158
LATE
(2)
— — — — — PORTE Data Latch Register
(Read and Write to Data Latch)
---- -xxx 50, 110
LATD
(2)
PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 50, 107
LATC PORTC Data Latch Register (Read and Write to Data Latch) xxxx xxxx 50, 104
LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 50, 101
LATA
— — PORTA Data Latch Register (Read and Write to Data Latch) --xx xxxx 50, 98
SSP2ADD MSSP2 Address Register in I
2
C™ Slave mode. MSSP2 Baud Rate Reload Register in I
2
C Master mode. 0000 0000 50, 158
SSP2STAT SMP CKE D/A
PSR/WUA BF 0000 0000 50, 150,
160
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 50, 151,
161
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 50, 164
GCEN
ACKSTAT ADMSK5
(3)
ADMSK4
(3)
ADMSK3
(3)
ADMSK2
(3)
ADMSK1
(3)
SEN 0000 0000 48, 163
PORTE
(2)
— — — — —RE2
(2)
RE1
(2)
RE0
(2)
---- -xxx 50, 110
PORTD
(2)
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 50, 107
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 50, 104
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 50, 101
PORTA
— —RA5— RA3 RA2 RA1 RA0 --0- 0000 50, 98
TABLE 6-3: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: See Section 5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”.
2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 16.4.3.2 “Address
Masking” for details.