Datasheet
PIC18F45J10 FAMILY
DS39682E-page 62 © 2009 Microchip Technology Inc.
TABLE 6-3: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 47, 53
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 47, 53
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 47, 53
STKPTR STKFUL STKUNF
— Return Stack Pointer 00-0 0000 47, 54
PCLATU
— — — Holding Register for PC<20:16> ---0 0000 47, 53
PCLATH Holding Register for PC<15:8> 0000 0000 47, 53
PCL PC Low Byte (PC<7:0>) 0000 0000 47, 53
TBLPTRU
— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 47, 74
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 47, 74
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 47, 74
TABLAT Program Memory Table Latch 0000 0000 47, 74
PRODH Product Register High Byte xxxx xxxx 47, 81
PRODL Product Register Low Byte xxxx xxxx 47, 81
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 47, 85
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 47, 86
INTCON3 INT2IP INT1IP
—INT2IEINT1IE— INT2IF INT1IF 11-0 0-00 47, 87
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 47, 67
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 47, 67
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 47, 67
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 47, 67
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A 47, 67
FSR0H
— — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 47, 67
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 47, 67
WREG Working Register xxxx xxxx 47
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 47, 67
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 47, 67
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 47, 67
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 47, 67
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A 47, 67
FSR1H
— — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 47, 67
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 47, 67
BSR
— — — — Bank Select Register ---- 0000 47, 58
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 48, 67
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 48, 67
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 48, 67
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 48, 67
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A 48, 67
FSR2H
— — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 48, 67
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 48, 67
STATUS
— — —NOVZDCC---x xxxx 48, 65
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: See Section 5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”.
2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 16.4.3.2 “Address
Masking” for details.