Datasheet

© 2009 Microchip Technology Inc. DS39682E-page 3
PIC18F45J10 FAMILY
Pin Diagrams (Continued)
44-Pin QFN
(1)
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/T0CKI/C1OUT
RB4/KBI0/AN11
RB3/AN9/CCP2*
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
V
DD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO1
RC4/SDI1/SDA1
RD3/PSP3/SS2
RD2/PSP2/SDO2
MCLR
RA0/AN0
RA1/AN1
RA2/AN2/V
REF-/CVREF
RA3/AN3/VREF+
V
DDCORE/VCAP
RA5/AN4/SS1/C2OUT
RE0/RD
/AN5
RE1/WR
/AN6
RE2/CS
/AN7
V
DD
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1/P1A
RC3/SCK1/SCL1
RD0/PSP0/SCK2/SCL2
RD1/PSP1/SDI2/SDA2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F44J10
40-Pin PDIP (600 MIL)
PIC18F45J10
* Pin feature is dependent on device configuration.
.
* Pin feature is dependent on device configuration.
Note 1: For the QFN package, it is recommended that the bottom pad be connected to V
SS.
10
11
2
3
6
1
18 19 20 21 22 12 13 14 15
38
8
7
44 43
42
41 40 39
16 17
29
30
31
32
33
23
24
25
26
27
28
36 34 35
9
PIC18F44J10
37
MCLR
RB7/KBI3/PGD RB6/KBI2/PGC
RB5/KBI1/T0CKI/C1OUT
RB4/KBI0/AN11
NC
RC6/TX/CK RC5/SDO1 RC4/SDI1/SDA1 RD3/PSP3/SS2
RD2/PSP2/SDO2 RD1/PSP1/SDI2/SDA2 RD0/PSP0/SCK2/SCL2 RC3/SCK1/SCL1 RC2/CCP1/P1A RC1/T1OSI/CCP2* RC0/T1OSO/T1CKI
OSC2/CLKO
OSC1/CLKI
V
SS
VDD
RE2/CS/AN7
RE1/WR
/AN6
RE0/RD
/AN5
RA5/AN4/SS1
/C2OUT
V
DDCORE/VCAP
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
V
SS
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2*
RD7/PSP7/P1D
5
4
VSS
VDD
VDD
RA3/AN3/VREF+
RA2/AN2/V
REF-/CVREF-
RA1/AN1 RA0/AN0
PIC18F45J10
= Pins are up to 5.5V tolerant
= Pins are up to 5.5V tolerant