Datasheet

© 2009 Microchip Technology Inc. DS39682E-page 45
PIC18F45J10 FAMILY
FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR
NOT TIED TO VDD): CASE 2
FIGURE 5-6: SLOW RISE TIME (MCLR
TIED TO VDD, VDD RISE > TPWRT)
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
0V
1V
3.3V
T
PWRT