Datasheet

PIC18F45J10 FAMILY

TABLE 24-25: A/D CONVERSION REQUIREMENTS

Param

No.

Symbol Characteristic Min Max Units Conditions

130 T

AD A/D Clock Period 0.7 25.0

(1)

μsTOSC based, VREF ≥ 2.0V

131 TCNV Conversion Time

(not including acquisition time) (Note 2)

11 12 TAD

132 TACQ Acquisition Time (Note 3) 1.4 — μs-40°C to +85°C

135 TSWC Switching Time from Convert → Sample — (Note 4)

Note 1: The time of the A/D clock period is dependent on the device frequency and the T

AD clock divider.

2: ADRES registers may be read on the following T

CY cycle.

3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (V

DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.

4: On the following cycle of the device clock.