Datasheet

© 2009 Microchip Technology Inc. DS39682E-page 327
PIC18F45J10 FAMILY
FIGURE 24-12: EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0)
TABLE 24-16: EXAMPLE SPI™ MODE REQUIREMENTS (CKE = 0)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SS
x ↓ to SCKx ↓ or SCKx ↑ Input TCY —ns
71 T
SCH SCKx Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 T
SCL SCKx Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TDIV2SCH,
T
DIV2SCL
Setup Time of SDIx Data Input to SCKx Edge 20 — ns
73A T
B2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TSCH2DIL,
T
SCL2DIL
Hold Time of SDIx Data Input to SCKx Edge 40 — ns
75 T
DOR SDOx Data Output Rise Time — 25 ns
76 TDOF SDOx Data Output Fall Time — 25 ns
77 T
SSH2DOZSSx ↑ to SDOx Output High-Impedance 10 50 ns
80 T
SCH2DOV,
T
SCL2DOV
SDOx Data Output Valid after SCKx Edge — 50 ns
83 T
SCH2SSH,
T
SCL2SSH
SS
x ↑ after SCKx Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDI
70
71 72
73
74
75, 76
77
78
79
80
79
78
SDIx
MSb LSb
bit 6 - - - - - - 1
MSb In
bit 6 - - - - 1 LSb In
83
Note: Refer to Figure 24-3 for load conditions.